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Lamp driver output voltage test. |
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|  MIL-C-64030 (AR)
4. 5.2.2.2.4 Clocks. Apply a square wave with a frequency of
478 Khz 10%, a logic zero level of 0 0.2 volts and a logic one
level of 5 0.3 volts to E43 (CLK) and the E45 (DLACK).
4.5.2.2.3 Logic voltage regulation test. Set the voltage on
E9 (VBT) from 10.4 0.1 volts to 14.4 0.1 volts. Use a
multimeter to verify that the voltage in both cases on E39 (+5V)
is in compliance with the requirements of 3.5.2.2.
4.5.2.2.4 Low voltage detect (LVD) test. Set the voltage on
E9 (VBT) to 11 0.5 volts, verify that E12 (BTOK) is "ON". Set
the voltage on E9 (VBT) to 10.35 0.05 volts.
Verify that E12
(BTOK) is "OFF" as specified in 3.5.2.4. Set the voltage on E9
(VBT) to 13 0.5 volts.
4.5.2.2.5 Lamp driver output voltage test.
4.5.2.2.5.1 Data accept test. Apply 5 0.1 volts to E42
(DA). Use a multimeter to measure the "ON" voltage at E12 (BTOK),
E16 (CTOK) and E15 (DALT) is "ON" as specified in 3.5.2.4.
4.5.2.2.5.2 Arm test. Remove the ground from E1O (VHV) and
apply 0 0.2 volts to E11 (S/A). Use a multimeter to verify that
E12 (BTOK), E16 (CTOK) and E15 (DALT) are "OFF" as specified in
3.5.2.4.
4.5.2.2.6 Hardwire input circuit holdoff test. At 285 2
seconds after applying O 0.2 volts to E11 (S/A) in 4.5.2.2.5.2,
apply a storage scope triggers pulse with an amplitude of 8 0.2
volts and a width of 1 0.1 milliseconds to E18 (HW1) with
respect to E17 (HW2). Use a multimeter to verify that the voltage
at E47 (HWD) is 0 0.2 volts and the voltage at E46 (-HWD) is 5.2
0.3 volts. Use the storage scope to verify that the waveform at
E50 (-FCL) meets the requirements specified in 3.5.2.8.
4.5.2.2.7 Hardware input circuit deploy test. At 315 2
seconds after applying O + 0.2 volts to E11 (S/A) in 4.5.5.2.5.2,
apply a storage scope triggers pulse with an amplitude of 8 0.2
volts and a width of 1 0.1 milliseconds to E18 (HW1) with
respect to E17 (HW2). Use a multimeter to verify that the voltage
at E47 (HWD) is 5.2 0.3 volts and the voltage at E46 (-WD) is
0.2 0.2 volts. Use the storage scope to verify that the
waveform at E50 (-FCL) meets the requirements specified in
3.5.2.10. vertify the following responses.
4.5.2.2.8 Deploy test. Apply the ADATA/DEP waveform of
figure 7 with a dummy address FSD pattern as described on Drawing
9333026 to E44 (ADATA) and E41 (DEP) simultaneously. Use a
storage scope to verify the following responses.
4.5.2.2.8.1 EBI pulses. With the EBI test load specified in
4.5.2.2.2.1 applied, verify that the EBI waveforms specified in
3.5.2.7 appear at the tube driver outputs.
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