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Page Title:
Magnetic Drum Memory to Drum Controller |
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|  MIL-L81347C(AS)
(3)
Data -8 Lines
(4)
Track Address -9 Lines
MDM Test Modes -4 Lines
(5)
Sector Begin - 1 Line
(6)
(7)
Sector End -1 Line
(8)
MDM Manual Test Inhibit -1 Line
(9)
MDC Test Mode Inhibit -1 Line
(10)
MDM SI (System Initialize) -1 Line
(11)
DAMS OTB2 (Out-of-Tolerance Bit) -1 Line
(12)
MDM Track Test Inhibit -1 Line
Magnetic Drum Memory to Drum Controller - Signals from the
3.5.4.4.4.3.3.6.2
MDM to the Drum Controller shall consist of the following:
(1)
Word Clock - 1 Line
Tachometer Pulse - 1 Line
(2)
Data - 8 Lines
(3)
(4)
MDM Status -6 Lines
Byte Parity Error - 2 Lines
(5)
Byte Clock - 1 Line
(6)
(7)
Preamble Detect -1 Line
(8)
MDM Test Error -1 Line
(9)
MDM Test Complete - 1 Line
(lo)
MDM Temp Sht Dn Status (Temperature Shut Down Status) -
1 Line (return isolated `from ground)
(11)
Bit Clk Tst (Bit Clock Test) - 1 Line
- Two calibrated
3.5.4.4.4.3.3.4.6.3
Mechanical Signature Analysis (MSA) Outputs
accelerometer shall be included as part of the drum subassembly for the purpose of
obtaining mechan-
ical signature analysis data. The accelerometers shall be located in close proximity
to the drum
bearings. Accelerometer outputs shall be provided and shall be located on the MDM
front panel.
Controller Power Signals - Power signals between the Drum
3.5.4.4.4.3.3.4.6.4
Controller and Magnetic Drum Memory shall be as follows:
(1) DAMS OTB 2 (DAMS tit-of-Tolerance Bit 2) - The MDM
shall have the capability of monitoring the DAMS 2 line. Whenever a Logic 1 l evel is present on
the DAMS OTB 2-line, the MDM shall process any write, read or test instruction. Whenever an open-
circuit condition is detected, the MDM shall go into an immediate standby condition which precludes
any further data processing activity or acceptance of control signals. Upon detection of a Logic 1
267
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