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MIL-G-435231 (AS)
Where LSB is "Least Significant Bit" and MSB is "Most Significant Bit, " the
aft antenna shall be selected if the third bit is a "one"; and the forward
antenna shall be selected if the third bit is a "zero. Eight spares shall be
provided for future growth. The last two bits shall be hardwired to a "zero."
30.2 Data. The data shall consist of a 16-bit parallel word with two bits
"Sync" and 12 bits of "Data" with the last two bits tied to "zero." The first
half of each bit shall be "Sync" with the second half of each blt data being a
"one" or "zero". For "Sync," the second half of each bit is "Sync." The
clock rate shall be 50 +4.4, -4.0 Hz.
30.3 Clock rate.  The clock rate shall be determined by the 1300 Hz voltage
controlled oscillator (VCO). The VCO sine wave output shall be converted to a
square wave and then divided by 26 to obtain a 50 percent duty cycle. During
standard conditions the clock rate is as follows:
or 50 0.2 Hz for a "Sync."
a.
b.
or 46.23 0.2 Hz for a "Zero."
or 53.77 0.2 Hz for a "One."
c.
During service conditions the clock rate is as follows:
a.
or 50M.62 Hz for a "Sync."
b.
or 46.23 0.62 Hz for a "Zero."
or 53.77 0.62 Hz for a "One."
c.
30.4 Data definition (standard and service conditions). The data shall be
defined for standard and service conditions as follows:
Standard conditions
a.
(1) A sync bit shall be defined as 1269 to 1331 Hz.
(2) A data zero shall be defined as 1197 to 1250 Hz.
(3) A data one shall be defined as 1351 to 1403 Hz.
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