1. Heavy current paths (I ≥ 0.05 A) are indicated by bold lines.
2. Kelvin connections must be used for all output current and voltage measurements.
For device types 03 and 04, output voltage measurements should be made at the case.
For device type 03 only. If output voltage measurements are not made at the case but instead at
the output lead, an error will result in the measurement due to internal lead resistance.
The amount of error depends on the magnitude of the load current and the distance from the case
to where the output voltage measurement is taken on the output pin.
3. The output offset voltage shall be adjusted to zero with the device under test (DUT) removed.
The operational amplifier stabilization networks may vary with test adapter construction.
Alternate drive circuits for the 2N6294 may be used to develop the proper load current and input
4. Relay switch positions are defined in table III.
5. Load currents of 5 mA may be established via the load resistors R1 and R2. All other load currents
shall be established via the pulse load circuits. Resistors R1 and R2 shall have a tolerance ≤ 0.1 %
for device types 01 and 02.
The pulse generator for the pulse load circuit shall have the following characteristics:
a. Pulse amplitude = -10 ( |IL| - VO / ( R1 + R2 )) volts (referenced to 5 volts).
b. Pulse width = 1.0 ms (unless otherwise stated).
c. Duty cycle = 2% (maximum).
Load currents shall be determined by the voltage measured across the 1 Ω resistor.
Measurements shall be made 0.5 ms after the start of the pulse.
VIN (LOW) and VIN (HIGH) per table III herein.
9. VRLINE = VB VA.
10. The output voltage is sampled at specified intervals. Strobe pulse width is 100 µs maximum.
11. |IL| (minimum) and |IL| (maximum) per table III herein.
12. VRLOAD = VD VC.
13. VRTH = VD VE.
IOS = (IL) amps.
For device types 01 and 02, t = 10.5 ms. For device types 03 and 04, t = 20.5 ms.
For static test VRLOAD 1, IL = 500 mA, device type 03 only the following may apply. If output voltage
measurements are taken from the output lead and not the case, the maximum limit shall be allowed
to increase by 5 mV to account for the error due to internal lead resistance.
FIGURE 9. Test circuit for static tests for device types 01, 02, 03, and 04 Continued.