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Microcircuits, Digital, TTL, Flip-Flops, Monolithic Silicon
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Microcircuits, Digital, TTL, Flip-Flops, Monolithic Silicon
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Terminal connections and logic diagrams.



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MIL-M-38510/2G
1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
A
GDFP5-F14 or CDFP6-F14
14
Flat pack
B
GDFP4-F14
14
Flat pack
C
GDIP1-T14 or CDIP2-T14
14
Dual-in-line
D
GDFP1-F14 or CDFP2-F14
14
Flat pack
E
GDIP1-T16 or CDIP2-T16
16
Dual-in-line
F
GDFP2-F16 or CDFP3-F16
16
Flat pack
1.3 Absolute maximum ratings.
Supply voltage range .............................................................................
-0.5 V dc to +7.0 V dc
Input voltage range ................................................................................
-1.5 V dc at -12 mA to 5.5 V dc
-65 to +150C
Storage temperature range ....................................................................
Maximum power dissipation, (PD)
flip-flop,  1/.......................................................................................
110 mW 1/
300C
Lead temperature (soldering, 10 seconds)..............................................
0.09C/mW for flat packs
Thermal resistance, junction to case (θJC):..............................................
0.08C/mW for dual-in-line pack
Junction temperature (TJ)........................................................................ 175C
1.4 Recommended operating conditions.
Supply voltage (VCC) .............................................................................. 4.5 V dc minimum to
5.5 V dc maximum
Minimum high-level input voltage (VIH) ................................................... 2.0 V dc
Maximum low-level input voltage (VIL) .................................................... 0.8 V dc
Normalized fanout (each output) 2/ ....................................................... 10 maximum
Case operating temperature range (TC) .................................................. -55 C to +125 C
Input set up time:
Device type 01, 02, 03 and 04, ......................................................... clock pulse width
Device type 05, 06, and 07................................................................ 20 ns
Input hold time
Device types 01, 02, 03 and 04......................................................... 0 ns
Device type 05, 06 and 07 ................................................................ 5 ns
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification.
This section does not include documents cited in other sections of this specification or recommended for
additional information or as examples. While every effort has been made to ensure the completeness of this list,
document users are cautioned that they must meet all specified requirements of documents cited in sections 3,
4, or 5 of this specification, whether or not they are listed.
_______
1/ Must withstand the added PD due to short circuit condition (e.g. IOS) at one output for 5 seconds
d
uration
2/ Device will fanout in both high and low levels to the specified number of IIL1/IIH1 inputs of the same device type
as that being tested.
2

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