A = Normal clock pulse.
B = Momentary GND, then 4.5 V.
C = This note has been deleted.
D = Momentary 4.5 V, then GND.
E = Momentary ground, then 2.4 V.
F = Momentary ground, then 5.5 V.
* After clock pulse apply 12 mA to clock pin to insure Q is still in the low state (see figure 15).
** Test time limit ≤100 ms.
1/ Terminal conditions (pins not designated may be H ≥ 2.0 V, or L ≤ 0.8 V, or open).
2/ Input voltages shown are: A = 2.0 V minimum and B = 0.8 V maximum.
3/ Output voltages shall be either: (a) H = 2.4 V, minimum and L = 0.4 V, maximum when using a high speed checker double comparator; or (b)
H ≥ 1.5 V and L < 1.5 V when using a high speed checker single comparator.
4/ Tests shall be performed in sequence.
5/ One normal clock pulse, then 4.5 V.
6 FMAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency.
7/ For CKT A, IIH3 limits are 0 to 120 µA.