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Page Title: Figure 2. Truth tables and timing diagrams.
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img
MIL-M-38510/306E
Device type 01
INPUTS
OUTPUTS
MODE
SERIAL
PARALLEL
CLEAR
CLOCK
QA
QB
QC
QD
S1  S0
LEFT  RIGHT
A
B
C
D
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L'
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
X
X
a
b
c
d
a
b
c
d
H
L
H
X
H
X
X
X
X
H
QAn
QBn
QCn
H
L
H
X
L
X
X
X
X
L
QAn
QBn
QCn
H
H
L
H
X
X
X
X
X
QBn
QCn
QDn
H
H
H
L
L
X
X
X
X
X
QBn
QCn
QDn
L
H
L
L
X
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H = high level (steady state)
L = low level (steady state)
X = irrelevant (any input, including transitions)
= transition from low to high level
a, b, c, d = the level of steady state input at inputs A, B, C, or D, respectively.
QA0, QB0, QC0, QD0 = level of QA, QB, QC, or QD, respectively, before the
indicated steady state input conditions were established.
QAn, QBn, QCn, QDn = the level of QA, QB, QC or QD, respectively, before the most
recent  transition of the clock.
Typical clear, load, right-shift, left shift, inhibit, and clear sequences.
FIGURE 2. Truth tables and timing diagrams.
15

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