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Page Title: Figure 2. Truth tables and timing diagrams Device type 09
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img
MIL-M-38510/306E
Device type 09
Internal
Output
Outputs
Parallel
Shift/
Clock
QH
Clear
Clock
Serial
load
inhibit
QB
A....H
QA
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
X
a....h
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
H = High level (steady state), L = Low level (steady state)
X = Irrelevant (any input, including transitions)
= Transition from low to high level
QA0, QB0, QH0 = the level of QA, QB, or QH respectively, before the indicated
steady state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent  transition of the clock;
indicates a one-bit shift.
FIGURE 2. Truth tables and timing diagrams - Continued.
22

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