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Page Title:
Table 3. Group A inspection for device type 01-cont. |
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|  FOOTNOTES:
A. Apply input pulse:
2.5 V minimum/5.5 V maximum
0V
B. VIN = 2.5 V.
C. VIN = 0.4 V.
D. Test numbers 59 through 111 shall be run in sequence.
E. Output voltages shall be either: (1) H ≥2.5 V minimum and L ≤0.4 V maximum when using a high speed checker double comparator: (2) H ≥1.5 V and L <1.5 V when using a high
speed checker single comparator.
F. fMAX minimum limit specified is the frequency of the clock input pulse. The output frequency shall be one-half of the clock input frequency. The input frequency on the AIN data shall
be one-half of the clock input frequency and the AIN shall be shifted such that the AIN ↑ and ↓ are coincident with the clock ↓ . Rise and fall times ≤ 6 ns. Input peak voltage 3 to 5
volts.
G. 3.0 V minimum/5.0 V maximum.
J. At the manufacturer's option, the following alternate procedure may be used to guarantee fMAX. Serial mode - fMAX for the serial mode shall be guaranteed by clocking the device four
times (after reset) at fMAX and looking for the QD output to toggle within three periods (3 x 1/ fMAX) plus allowed propagation delay. Two tests are performed, depending on the state of
the data input, to guarantee both LH and HL transition of the output pulse.
1/ This pulse must occur after the clear pulse.
2/ IIL limits (mA) min/max values for circuits shown:
Parameter
Terminal
A
B
C
D
E
F
G
IIL1
CLR
-.16/-.4
-.11/-.35
-.16/-.4
-.12/-.35
-.12/-.36
-.12/-.36
-.16/-.4
"
-.11/-.35
"
-.16/-.4
-.105/-.345
"
"
IIL2
S/R, AIN, BIN
CIN, DIN, S/L
IIL3
S0, S1
"
-.03/-.3
"
-.12/-.36
-.12/-.36
"
"
IIL4
CLK
"
-.03/-.3
-.20/-.44
-.12/-.36
-.12/-.36
"
-.15/-.38
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