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TABLE III. Group A inspection for device type 08 - Continued.
Terminal conditions (pins not designated may be high 2.0 V; or low 0.7 V; or open).
MIL-STD-
Cases E, F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Measured
Limits
Unit
terminal
Subgroup
Symbol
883
Cases 2, X
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
method
Test no.
Shift
CLK
E
F
G
H
Serial
A
B
C
D
CLK
VCC
Min
Max
GND
QH
QH
Load
INP
INHB
10
fMAX
91
20
MHz
TC = 125C
tPLH5
3003
92
5
52
ns
tPHL5
See
93
"
"
"
tPLH5
fig. 11
94
"
"
"
tPHL5
95
"
"
"
Same tests and terminal conditions as subgroup 9, except TC = 125C.
tPLH1
96
"
58
'
tPHL1
97
"
"
"
tPLH1
98
"
"
"
tPHL1
99
"
"
"
tPLH3
100
"
39
"
tPHL3
101
"
46
"
tPLH4
102
"
46
"
"
tPHL4
103
39
"
Same tests, terminal conditions, and limits as subgroup 10, except TC = -55C.
11
TC = -55C
NOTES:
2/ A = 2.5 V and B = 0.4 V.
3/ Output voltages shall be either:
(a) H = 2.5 V minimum and L = 0.4 V maximum when using a high speed checker double comparator or,
(b) H 1.5 V and L 1.5 V when using a high speed checker single comparator.
4/ fMAX minimum limit specified is the frequency of the clock input pulse. The output frequency
shall be one-half of the input clock frequency. The input frequency on the serial shall be one-half
of the clock input frequency and the serial shall be shifted such that the serial  and  are coincident
with the clock  , but may be offset sufficiently to assure adequate tSETUP and tHOLD. Rise and fall times
6 ns. Input peak voltage 3 to 5 volts.
1/ IIL limits (mA) min/max values for circuit shown:
Parameter
Terminal
A
C
F
IIL1
CLK, CLK/INHIB
-.001/-.150
-.12/-.38
-.005/-.72
IIL6
A,B,C,D,
-.120/-.360
-.12/-.38
-.12/-.38
E,F,G,H
S/IN
-.100/-.340
-.12/-.38
-.12/-.38
IIL7
S/L
-.001/-.150
-.36/-1.08
-.005/-.72

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