Click here to make tpub.com your Home Page

Page Title: Figure 5. Synchronous switching test circuit (high level data) type 04.
Back | Up | Next

Click here for thousands of PDF manuals

Google


Web
www.tpub.com

Home

   
Information Categories
.... Administration
Advancement
Aerographer
Automotive
Aviation
Construction
Diving
Draftsman
Engineering
Electronics
Food and Cooking
Logistics
Math
Medical
Music
Nuclear Fundamentals
Photography
Religion
   
   

 




img
MIL-M-38510/372B
NOTES:
1. Clock input pulse characteristics: t1 = t0 = 6 1.5 ns; tP(CLK) = 16.5 ns; PRR 1.0 MHz.
2. D input pulse characteristics: t1 = t0 = 6 1.5 ns; t(SETUP) = 10 ns; t(HOLD) = 4 ns; tP = 14 ns;
PRR is 50% of clock PRR.
3. For fMAX, the clock input pulse characteristics are as follows: t1 = t0 3 ns; for 25C, tP(CLK) = 14 ns; PRR = 35
MHz; for -55/125C, tP(CLK) = 16.5 ns, PRR = 30 MHz. The D input pulse shall be one-half of the frequency of
the clock and the D and shall be coincident with the clock , but may be offset sufficiently to assure
adequate tSETUP and tHOLD (see 1.4). t1 = t0 3ns.
4. Inputs not under test are at ground.
5. CL = 50 pF 10%, including scope probe, wiring, and stray capacitance without package in test fixture.
6. RL = R1 = 4991%.
7. Voltage measurements are to be made with respect to network ground terminal.
FIGURE 5. Synchronous switching test circuit (high level data) type 04.
19

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc. - A (SDVOSB) Service Disabled Veteran Owned Small Business