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|  MIL-N-81604C(AS)
Para 3.4.4.2
(cent)
d.
Sin Lat/Mag Slave Hdq Error - This input to the
*
IMU is an analog d-c signal from the CAU which
causes the stable element to torque in azimuth when
the equipment is in the backup attitude reference
mode (magnetic slave or free). This input shall
only affect the IMU when the Attitude Reference
discrete is in the true state. Earth rate times
the sine of latitude should be provided in the
*
Free mode, and magnetic slaved heading error should
*
be provided in Magnetic Slaved mode. The receiver
in the IMU shall be a differential amplifier with
*
a differential impedance of 40K ohms (minimum).
Either input to the receiver shall have an imped-
*
ance to ground of no less than 20K ohms. For
linear operation, the receiver shall accept a max-
*
imum of 10 volts d-c. The input scale factor
*
shall be 10 degrees/hour/volt 1 percent (1 sigma).
Zero volts shall be zero degrees/hour. A positive
voltage shall cause the platform heading angle to
increase.
3.4.4.3 ANCU/CAU Interface
3.4.4.3.1 Serial Interface - There shall be two modes of oper-
ation of this interface: Data mode and ANCU request mode.
Clocking for data transmission between units in this interface
shall be supplied by the CAU. This clock after being received
and restored in the ANCU shall be retransmitted to the CAU to
be used for clocking data received by the CAU from the ANCU.
All data transmission between units shall be under control of
*
the CAU. Negative number output from the ANCU shall be in two's
*
complement form. The ANCU/CAU serial interface timing diagram
*
is presented in figure 10. Figures 11 and 12 present the ANCU
*
data mode and ANCU request mode timing diagrams, respectively.
Data Mode - There shall be three different opera-
a.
tions that can occur in this mode. The first shall
be transmission from CAU to ANCU of a 12-bit word
causing the interface to interrupt the computer to
a specified address. The second shall be trans-
mission from the CAU to the ANCU of 40 bits consist-
ing of a 12-bit command-address word followed by
28 bits of data. This operation shall cause the 28
bits of data to be interleaved into memory at the
location specified by the address. The third
54
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