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|  MIL-N-81604C(AS)
3.5.4.3 Arithmetic Unit - The ANCU shall have the following .
maximum computational speeds with a 28-bit operand:
8 microseconds for primary instruction,
Add time:
4 microseconds for secondary instruction
58 microseconds
Multiply time:
110 microseconds
Divide time:
The ANCU shall have a minimum clock rate of 2 MHz. Each instruc-
tion word shall contain two instructions which shall be executed
as a sequential pair.
3.5.4.4 Input/Output - The I/O section of the ANCU shall pro-
vide the buffering and control of data and addresses required
for computer communication defined in 3.4.4.1 (IMU), 3.4.4.4
(CIU), 3.4.4.3 (CAU), 3.4.3.2 (External), and 3.4.4.5 (PSU
interface) . As a minimum, the I/O unit shall contain the follow-
ing functional components:
a.
A 28-bit (minimum) output buffer register
which communicates serially or in parallel
with the required units.
b.
A 10-bit (minimum) external device address
register which receives the device address
from the computer.
c.
A 15-bit (minimum) parallel address input
channel to the memory address register for
memory access either of interrupt instruc-
tions or of interleave data.
d.
A 28-bit (minimum) parallel data input
channel to the memory buffer register for
memory interleave input data.
e.
A 28-bit (minimum) parallel data output
channel from the memory buffer register
for memory interleave output data.
f.
A real time counter which is capable of
being set or read from the output buffer
register.
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