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|  MIL-N-81604C(AS)
Appendix I
Para 30.5.8.2
(cont)
*
figure 38. The maximum delay of the leading
edge of the first data bit with respect to the
leading edge of the message gate shall be 200
nanoseconds.
In addition, the message request *
signal shall return to its false state within
10 s of the leading edge of the message gate.
In the event that the CP message request appears
concurrently with a CIG message request, the
CP request shall have first priority.
In addi-
tion, the ID code for this message shall be a
"l" in bits 63 and 64.
b.
CPI Requests - The CAU shall initiate two
message requests to the CP as a result of
receiving the proper 6-bit request code on
ANCU Data 2 (table XXIII). The CP shall respond *
within 300 s with a 32-bit message gate and
-
message in response to each request. The message
request signals shall return to their false
state within 10 S of the leading edge of their
respective message gates. The second message
request shall be generated automatically within
200 S of the trailing edge of the first mes-
sage gate. The message gates shall be synchro-
nous with the CP selected clock which shall be
used in clocking each 32-bit message into the
CAU with the maximum delay of 200 ns from the
leading edge of the first data bit with respect
to the leading edge of the message gate. The
messages shall be transmitted to the CAU, MSB
first, in the format shown in figure 38. Each
32-bit message shall go through a three-bit
delay in being shifted into the first 27-bit
positions of the CAU serial data register.
Each message will then be serially shifted out
of the serial data register, MSB first, to the
ANCU via Data 1 for interleave into memory.
*
Refer to 3O.5.10.1.
CP Message Request In - This message request
c.
from the CP shall be answered by the CAU with a
message gate and a message. Refer to 30.5.8.2a. *
The CAU line receiver shall be a Type 1 circuit.
CP Message Gate Out - This message gate from
d.
the CAU shall bracket all bits in the CP Message
out. Refer to 30.5.8.2a. The CAU line driver *
shall be a Type 2 circuit.
170
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