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|  MIL-N-81604C(AS)
Para 30.5.9.2
Appendix I
(cont)
k.
Vertical Reliability No. 2 - This discrete
output from the CAU to the RAI shall be identical *
.
to vertical Reliability No. 1 (refer to
30.5.9.2j) except that the relay contacts shall *
have a 26-volt rms, l-ampere capacity.
Vertical Reliability No. 3 - This discrete
l.
output from the CAU to the RAI shall be identical
*
to Vertical Reliability No. 2 (refer to
30.5.9.2k).
30.5.10 CAU/ANCU Interface
30.5.10.1 CAU/ANCU Serial Interface - Refer to 3.4.4.3.1 for a *
description of the CAU/ANCU serial interface operation and signal
Figure 39 describes the CAU serial interface timing *
description.
requirements.
Clock 1 (CAU to ANCU) - A 6-MHz square wave clock
a.
(83 20 ns pulse width) from the CAU shall be
supplied to the ANCU. The CAU line driver shall
be a Type D circuit.
Clock 2(ANCU to CAU) - A restored 6-MHz clock
b.
from the ANCU to the CAU shall be derived for
Clock 1. The CAU line receiver shall be a Type
D circuit.
Sync (CAU to ANCU) - An envelope from the CAU
c.
to the ANCU shall be supplied for gating data
to or from the ANCU. The CAU line driver shall
be a Type D circuit.
Data 1 (CAU to ANCU) - Data (to be interleaved
d.
into the ANCU memory) shall consist of data
words from internal CAU operations or external
avionics. The data formats and address assign-
ments of the 40-bit messages on Data 1 shall
*
conform to table XXV. Data to be interleaved
out of the ANCU memory shall be initiated by
the 12-bit command address messages on Data 1
*
conforming to table XVI. The CAU line driver
shall be a Type D circuit.
179
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