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|  MIL-T-81782C(AS)
c.
Memory unit interface
Power supply-storer (PS/S) interface
d.
3.4.2.1.3 Interrupt and status tests. The response of the computer to
external interrupt signals and control shall be verified.
3.4.2.2 Memory Unit MU-588( )/AWG-9 tests. Operation of the memory
unit shall be verified by performance of the following tests.
3.4.2.2.1 Address decode. Word and plane address decodes in the memory
unit shall be verified by selection of predetermined locations.
3.4.2.2.2 Memory unit control. Word and plane enable tests shall be
performed to verify the memory control.
3.4.2.2.3 Memory unit storage. The capability shall be provided to
write test patterns into the memory unit, accomplish the preread opera-
tion, and read and verify the test data.
3.4.2.2.4 Load and verify tactical program. The capability shall be
provided to write the tactical program into the memory and to verify the
program by matching all data, bit by bit against the tactical/BIT tape,
or if a memory unit write has not been performed, to verify the stored
tactical/BIT program by matching all data, bit by bit, against the tactical/
BIT tape.
3.4.2.3 Processor, Data CV-3151( )/AWG-9 and CV-3165( )/AWG-9 tests.
Operation of the data processor shall be verified by performing the
following tests.
3.4.2.3.1 BIT verification. Tests shall be performed to verify proper
operation of the data processor self-test circuitry in the WRA under test.
3.4.2.3.2 Interface tests. Each of the following interfaces shall be
functionally tested to verify proper operation of the data processor.
a.
Program controlled channel - The CTS shall test the data
transfers to and from the computer via the program con-
trolled channel.
b.
Data processor controlled channel - The CTS shall test
the data transfers to and from the computer DRO memory
via the data processor controlled channel.
c.
Interrupt channel - The CTS shall test the data processor
generated interrupt signals. The interrupts to be tested
shall include the following operational and tactical
interrupts:
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