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Page Title:
Converter-Interface Uuit Processed Interrupts |
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| MIL-W-85057(AS)
(2) + 10 Vdc reference No. 2: 75 mA, maximum.
- 10 Vdc reference: 75 mA, maximum.
(3)
3.5.2.1.5.2 Maximum Reference Voltage. The reference voltages applied
to associated equipment shall not exceed 14 V under all conditions of no
load or internal power supply regulator failure, except that the maximum
reference voltage applied to the Normal Accelerometer (see 6.6) shall not
exceed + 13 V.
I
3.5.2.2 Converter-Interface Uuit Processed Interrupts. Priorities
for Interrupt levels "2" and "3" shall be established by the CIU and provided
to the DC as an external Interrupt request which will cause a "break-in"
to the main store location "3". A level "2" interrupt shall have hardware
priority over level "3" interrupts only if both occur at the same instant
or are pending when interrupts are enabled. The priority scheme shall be
implemented with a programmable mask which enables/disables individual
Interrupts as bits in the mask are set to logical "1" or "O". The mask
shall be readable and loadable by the program. Once an interrupt request
has been acknowledged by the DC, all interrupts, levels "2" and "3", will
be inhibited and a l6-bit data tag sent to the DC identifying the interrupt
level as shown below:
(1) Priority level "2" (highest external priority order in CIU).
a . ISW bits - 3
b. Linkage (HEX) 21
c. Maskable.
(2) Priority level "3".
a. ISW bits 4 - 7
b. Linkage (HEX) 212
c. Maskable.
Interrupt requests shall remain inhibited until a Branch Out (BO)
unconditional instruction is executed. Interrupt requests shall
also be inhibited for a period of 40 to 60 following a data output
to load the mask, unless BO iS executed during this period, in which
.
case the time period will be terminated and Interrupts enabled.
3.5.2.2.1 Converter-Interface Unit Supplied Interrupt Status Work (ISW).
Interrupt levels "2" and "3" shall be identified in the CIU by means of
an ISW. The allocation of bits in the ISW shall be as given below. The
ISW shall be readable and bits independently resettable by the program.
Interrupts will be accepted by the CIU even when interrupt requests to
the DC are Inhibited.
-39-
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