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|  MIL-W-85057(AS)
ISW BIT
A-REG BIT
Identificatlon
Priority Level
8
PROGRAM COUNTER NUMBER 2
0
2
(12 BIT)
1
PROGRAM COUNTER NUMBER 1
9
2
(16 BIT)
2
10
Go/No-Go
2
SPARE
11
3
2
4
CONVERSION COMPLETE
12
3
5
13
BUFFERED I/0 COMPLETE
3
6
14
SPARE
3
3.5.2.2.2 Real Time Clock (PLC 2). Within the CIU, there shall be a
real time clock that decrements with a frequency of 50 kHz and an accuracy
of + 1 count in 10,000 or better. The counter shall be configured to allow
generation of an interrupt at the lapse of a period between 100 s and 80 ma.
The current value of the counter shall be readable under program control.
The counter shall be disabled by a "reset interface" signal and shall remain
so until loaded by program control. Upon reaching zero, the counter will
generate a level "2" interrupt, roll over to its maximum value, and continue
to decrement. The interrupt shall be inhibited under program control by
masking the interrupt. It shall be possible to maintain l measure of real
time within the computer of 100 ppm or less over a 2-hour period. .
.
3.5.2.2.3 Internal Timer (PLc 1). Within the CIU, there shall be
provided a down counter that can be loaded under program control to any
value from 20 s to 1.3 seconds. When the counter lapses to zero, a
level "2" interrupt shall be generated and than discontinue operation.
The counter is reactivated by reloading. When reloadad, the counter
shall count down with a frequency of 50 kHz and an accuracy of at
least + 1 count in 10,000. The interrupt shall be inhibited under
program control by masking the Interrupt.
3.5.2.2.4 GO/NO-GO (Watchdog) Timer. Within the CIU, there shall
be a readable timer that measures a time equivalent to 1.3 seconds with
an accuracy of at least + 1 count in 10,000. This timer shall run whenever
the computer is powered and not in manual control. The timer shall be
resettable under program control and, when the time period lapses, a
level "2" interrupt shall be generated. The current value of the counter
shall be readable under program control. Upon issuing the interrupt,
the counter shall continue tO increment. The Interrupt shall be inhibited
under program control by masking the interrupt.
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