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|  MIL-C-50743(MU)
8 August 1973
4.6.5 Target selection and reset test. Connect J1-j to J1-e and
J1 -f to J1 -k apply the input conditions of table III items 1 through 11
sequentially, measure the corresponding outputs at the listed output pins
of J1 and observe the corresponding readouts on the Circuit Assembly:
11737350 (Readout) to determine compliance with 3.3.1.4.
4.6.6 Minimum range inhibit test. Connect J1-j to J1-e and
J1-f to J1-k, apply the logical one type-B signal of table I to J1 -h, J1-AA,
and J2-h, apply the logical zero type-B signal of table I to J1-q, J1-g,
and J1-z and remove the unit cover to release switch S1 on the Circuit
Card Assembly: 10559295 (Reply Gating). Observe the output at J@-f
to determine compliance with 3.3.1.5.
4.6.7 A-trigger and video test. Apply the digital type-B signal
of table I as follows:
a. Logical zero to J1-q, J1-n and J1-p
b. Logical one to J1-AA, J1-z, J1-m, and J2-h
c. Momentary Logical zero to J1-t, J1-AA, and J1-s
d. Logical zero to J1-z
e. Voltage of J1-r to read +4.2 1.3 V
f. The waveforms of figure 5 as specified.
Observe the readout on the Circuit Card Assembly: 11737350 (Readout)
to determine compliance with 3.3.1.6.
4.6.8 Test access output test. Apply the digital type-B signals
of table 1 to the input pins as specified for the items of table IV, and
measure the outputs at J5-m or J5-n, as applicable, to determine com-
pliance with 3.3.1.7.
4.6.9 PFN change test. Apply the load (item 1.6 of table I),
logical one digital type-B signal of table I to J1-q, J2-h, and J2-d, and
primary power (item 2.1 of table I). Momentarily apply a logical zero
type-B signal to J1 -t after application of primary power. Observe the
output signals at J1 -w and J1 -A to determine compliance with 3.3.1.8.
4.6.10 PFN voltage programmin test. Adjust the PFN voltage at
J3-A to +1200 15 V by means of control R10 on the Power Supply: 10559345
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