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|  MIL-C-70491(AR)
TABLE 1.
Display\p rocessor circuit card assembly
connector contacts.-Continued
P1
A47
EOF
B47
EOF
P1
A48
320Hz
B48
320Hz
P1
A49
CNTRST
B49
+35V
P1
A50
B50
GND
3.2
Performance.
3.2.1 General. The performance of the display\processor
circuit card assembly shall be in accordance with the following
requirements.
3.2.1.1 Functional. The display/processor circuit card
assembly shall be attached to the Computer Automation CA8200
tester or equivalent, using the connections as specified in Table
IV and pass the test patterns induced by Test Station
Software-Display/Processor CCA:
9379253.
3.2.1.2 Memory read cycle. A memory read cycle from either
,
RAM or EPROM shall be accomplished by applying the signals
specified in Figure 2 and Table I.
3.2.1.3 RAM write cycle. A RAM write cycle shall be
accomplished by applying the signals specified in Figure 3 and
Table I.
3.2.1.4
EPROM program cycle. An EPROM program cycle shall be
accomplished by applying the signals specified in Figure 4 and
Table I.
3.2.1.5 EPROM erasure. The EPROM shall be considered to be
erased when hexadecimal memory locations (0000) to (3FFF) contain
data (FF).
3.2.2 Physical characteristics. The physical characteristics
9
shall be as prescribed by the drawings, specifications, and QAP S.
3.2.3 Reliability. When specified in the contract, a special
sample shall be subjected to reliability testing. The
manufacturing and production techniques emloyed in the fabrication
of the display/processor circuit card assembly shall not degrade
the inherent reliability. The inherent reliability shall not be
less than 59,385 hours Mean Time Between Failures (MTBF).
(See 4
and 6)
3.3 Environmental. The display/processor circuit card
assembly shall meet the requirements specified herein unless
otherwise specified.
6
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