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|  MIL-D-70789A (AR)
The DRU shall not be damaged or malfunction when signal circuits
are connected or disconnected with power on or off.
3.5.4.4.1.1 Loqic levels. A binary logic "1" or "set"
condition shall be represented by a positive voltage on the "Hi"
line with respect to the "Lo" line. A logic "O" or "reset"
condition shall be represented by a positive voltage on the "Lo"
line with respect to the "Hi" line.
3.5.4.4.2 Data bus characteristics. The DRU shall have two,
independent, hi-directional, half-duplex, synchronous, serial
data buses. The two buses are labeled Main and Auxiliary. All
commands and messages shall be transferred between the prime
system and DRU via the data buses. Either bus may be used
separately or both may be used simultaneously. The electrical
characteristics, data protocols and data formats are the same for
both data buses. The only difference between the two buses is
that DRU response to data entry and mode change commands received
over the Auxiliary Bus can be inhibited by the prime system using
the Main bus (3.5.4.4.3.5). The data rate shall be 38.4 kilobits
per second. Each data bus input/output shall be in a receive
mode unless data is being transmitted by that particular bus.
The DRU shall return a data bus to the receive mode and be able
to receive a command, on the same data bus, within 1.0
millisecond after sending the end of the last bit of a message.
The DRU shall not start sending a message until at least 1.0
millisecond has elapsed after receipt of the end of the last bit
of the command which initiated the message.
3.5.4.4.2.1 Data Protocols. All serial data bus timing and
data protocols shall be compatible with the Zilog 28030 Serial
Communication Controller (SCC) used in the normal Synchronous
Data Link Control (SDLC) mode. Data shall change after the
falling edge and be valid on the rising clock edge. Prior to
transmission of a command or message, the Cyclic Redundancy Check
(CRC) generator and checker in the SW shall be preset to all
"1"s.
3.5.4.4.2.2 Data encoding. All serial data bus data shall
be encoded in the Non-return-to-Zero (NRZ) format compatible with
the Zilog Z8030 SCC.
3.5.4.4.2.3
Clock. The DRU serial data buses shall operate
properly when provided with 38.4 KHz + 0.01 percent, symmetrical
squarewave clock signals compatible with the Zilog Z8030 SCC used
in the normal SDLC mode.
3.5.4.4.3 Command and message characteristics. Commmands to
and messages from the DRU on either the Auxiliary or the Main Bus
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