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Page Title:
Maintenance .Control Panel Logic to Auxiliary Display Logic |
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|  MIL-D-81347C(AS)
3.5.4.4.3.4.1
General
3.5.4.4.3.4.1.1
Maintenance .Control Panel Logic to Auxiliary Display Logic -
The ADL shall receive the following signals from the MCPL.
(1) Output Data - Data words which will be received from the
computer via the MCPL shall command the timing, control, deflection, diagnostic instruction, and
video signals for the ADL. These signals will be a 30-bit data word and will adhere to the word formats
shown in Figures 142 through 146.
(2) Clocks - The MCPL shall transmit the 1.536 MHz clock and
400 Hz clock signals to the ADL.
The 400 Hz clock shall be derived from the AC 400 Hz Logic Unit 4
Input Power.
(3) Sync Control - The MCP sync switch shall Provide two
signals to the ADL:
(a) Continuous Sync
(b) Single Sync
(4) ON LINE - The MCPL shall provide a signal to the ADL
which shall inform the ADL that computer channel 13 is in an MCP test mode.
3.5.4.4.3.4.1.2
Data Multiplexer Subunit to Auxiliary Display Logic - The ADL
will receive two computer acknowledge signals from the DMS.
(1) Output Acknowledge - The DMS channel 02 Output Acknowl-
edge signal will indicate data on the output data lines is ready for sampling by the ADL.
(2) Input Acknowledge - The DMS channel 02 Input Acknowledge
.
signal will indicate the computer has sampled the ADL IDR or EI word.
Auxiliary Display Logic to the Data Multiplexer Subunit - The
3.5.4.4.3.4.1.3
ADL shall send the following signals to the DMS:
Input Data - The ADL shall transmit Diagnostic data to the
computer via the DMS using the IDR/IA mode of data transfer.
(2) Computer Requests - The DMS shall receive an Input Data
Request Signal from the ADL when the ADL has Input Data available. The ADL shall generate an
Output Data Request (ODR) to the DMS when it is ready to accept diagnostic instruction or display data.
(3) External Interrupt - The ADL shall transmit an External
.
Interrupt signal to the DMS whenever the 40 Hz sync pulse is generated in the ADL.
l
Auxiliary Display Logic to Auxiliary Display
3 . 5 . 4 .4.3.4.1.4
(1) "X' and "Y" Full Scale Deflection - Circuitry in the ADL
shall be capable of accepting digital data that describes positions, straight lines, circles, and char-
acters. This data shall generate waveforms which shall be transmitted to the horizontal and vertical
deflection circuits of the Auxiliary Display. The signal level shall be from O to between 6 to 8 volts
peak amplitude for a beam deflection of one radius. Step settling time for the Auxiliary Display shall
be no greater than 18 microseconds for full screen deflection. The sinusoidal signals for vector and
circle functions shall be 12 KHz, and character deflection axis bandwidth products shall be 110 KHz
minimum.
Circuits shall be provided in the ADL that shall limit the sum-
mation of the character signals, sinusoidal signals. and positioning signals from exceeding one display
radius along any coordinate axis in order to prevent overdriving the display deflection amplifiers.
Limiting of the maximum allowable X and Y deflection signals shall be at X and Y deflection amplitude
values of +6 to +8 Vdc +10% -0%.
246
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