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Page Title:
Appendix II. Input Amplifier Circuit Characteristics |
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|  MIL-D-81347C(AS)
APPENDIX II
INPUT AMPLIFIER CIRCUIT CHARACTERISTICS
SCOPE
1.
This Appendix defines the characteristics for the Input Ampli-
1.1
fier circuit referenced throughout this Specification.
REQUIREMENTS
2.
Voltage Level Inputs - The logic "1" state shall be O volts l O. 5
2.1
volt and the logic "0" state shall be 2.5 to 5.0 volts as measured at the input terminals of the input
amplifier. If both inputs of the input amplifier are disconnected this shall be considered a logic "O".
Input Noise Rejection - The circuit shall be capable of handling
2.2
common mode voltages of l 5 volts peak at the input terminals with no change in output level.
Input Impedance - The AC input impedance shall be 130 ohms
2.3
nominal and the DC input impedance shall be 2000 ohms nominal.
Voltage Level Outputs - The logic "1" state shall be 4.0 to 5.5
2.4
volts and the logic "0" state shall be 0 volts 0.5 volt.
Output Rise and Fall Times - The time required for the input
2.5
amplifier circuit to switch logic levels, as measured from the 10% to 90% amplitude points at the out-
put terminals of the amplifier shall be less than 0.5 microsecond when loaded as described in 2.7.
Output Propagation Delay - The propagation delay when loaded
2.6
as described in 2.7 shall be less than 00 ns.
Output Loading- The circuit shall be capable of sinking to
2.7
ground at least 10 milliamperes of current and driving a capacitive load of 50 pf at both output ter-
minals.
Environmental Performance - The circuit shall operate within
2.8
performance limits when subjected to temperatures over the range of -55C to +100C.
341/342
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