Integrated Circuit, Digital, CMOS Control and Timing Base, Monolithic, Silicon

• Integrated Circuit, Digital, CMOS Control and Timing Base, Monolithic, Silicon
• Requirements
• Design and Construction
• Table I - Maximum Rating
• Test Pattern
• Power Supply Requirements
• Figure 1. typical Construction
• Figure 1A. Input Pulse Pattern Generator
• Sequential Operation
• Figure 2. Sequential Operation
• Figure 3. Input/Output Waveform
• Figure 4
• High Temperature Storage
• Quality Assurance Provisions
• Table III. Qualification Test
• Table III. Qualification Test - Cont'd
• Table III. Qualification Test - Cont'd
• Table III. Qualification Test - Cont'd
• Classification of Inspections
• Table IV. Quality Conformance Test
• Figure 5
• Figure 7 "1" Output Voltage Test
• Figure 8 "O" Output Voltage Test
• Figure 9 LVD Voltage Test
• Figure 12 "1" Output Voltage Test, Terminal II
• Figure 14 Dynamic Burn-In Test
• Figure X. Feed-Back Signal Test
• Inspection Lot Formation (Lot Identification)
• Submission Of Inspection Equipment Designs for Approval
• Instructions
• Standardization Document Improvement Proposal
• Blank Pages

Integrated Circuit, Digital, CMOS Control and Timing Base, Monolithic, Silicon

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