Integrated Circuit, Digital, Cmos Logic Array Monolithic Silicon

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Integrated Circuit, Digital, Cmos Logic Array Monolithic Silicon

Integrated Circuit, Digital, Cmos Logic Array Monolithic Silicon
Requirements
Static Charge Protection
Figure 1. Typical Construction
Figure 2. Pin Assignment
Table I. Maximum Rating
Electrical Tests
Table II. Performance Characteristics: T= 25C
Table II. Performance Characteristics: T= 25C - Cont'd
Table III. Test Pattern
Table III. Test Pattern - cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Table III. Test Pattern - Cont'd
Flourocarbon Gross Leak
Quality Assurance Provisions
Inspection to be Performed
Table IV. Qualification Test
Table V. Quality Conformance Test
Preparation for Delivery
Figure 3. Leakage Current Test
Change in Manufacturing Prodcess
Subject Term (Key Word) Listing
Instructions
Standardization Document Improvement Proposal

Integrated Circuit, Digital, Cmos Logic Array Monolithic Silicon

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