Modules, Standard Electronic,Gate, NAND, Digital, Key Code BDA

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Modules, Standard Electronic,Gate, NAND, Digital, Key Code BDA

Modules, Standard Electronic,Gate, NAND, Digital, Key Code BDA
Correlation Requirements
Figure 1. BDA module function diagram, twelve 2-input NAND gates
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Order of Testing
Table II. Input to output relationship for each NAND gate
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. Zener applied potential test
Table III. Zener applied potential test (cont)
Figure 5. Zener applied potential test circuit for table III
Figure 5. Zener applied potential test circuit for table III (cont)
Table IV. VOUT (low-loaded) test
Figure 6. VOUT (low-loaded) test circuit for table IV
Table V. Isolation and continuity test
Figure 7. Isolation and continuity test circuit for table V
Table VI. Output voltage (high-level and low-level) test
Table VI. Output voltage (high-level and low-level) test (cont)
Figure 8. Output voltage (high-level and low-level) test circuit for table VI
Table VII. Output short circuit current test
Table VIII. Input current (low-level and high-level) test
Table VIII. Input current (low-level and high-level) test (cont)
Table VIII. Input current (low-level and high-level) test (cont)
Figure 9. Input current (low-level and high-level) test circuit for tables VII and VIII
Table IX. Input capacitance test
Table IX. Input capacitance test (cont)
Figure 10. Input capacitance test circuit for table IX
Table X. Power supply current (high-level and low-level) test
Figure 11. Power supply current (high-level and low-level) test circuit for table X
Figure 12. Power supply transient rise time test circuit for table XI
Figure 13. Power supply transient rise time test circuit waveforms for table XI
Table XII. Output pulse amplitude (high-level and low-level) test
Table XII. Output pulse amplitude (high-level and low-level) test (cont)
Table XIII. Transition time (tTHL and tTLH) test
Table XIII. Transition time (tTHL and tTLH) test (cont)
Table XIV. Propagation delay time (tPLH and tPHL) test
Table XIV. Propagation delay time (tPLH and tPHL) test (cont)
Figure 14. Output pulse amplitude, transition time and propagation delay time test circuit for tables XII, XIII and XIV
Figure 15. Output pulse amplitude, transition time and propagation delay time test circuit waveforms
Figure 16. BDA Logic load circuit
Table XV. Output crosstalk (high-level and low-level) test
Table XV. Output crosstalk (high-level and low-level) test (cont)
Figure 17. Output crosstalk (high-level and low-level) test circuit for table XV
Figure 18. Output crosstalk (high-level and low-level) test circuit waveforms for table XV
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic,Gate, NAND, Digital, Key Code BDA

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