Modules, Satndard Electronic, Gate, NAND, Digital, Key Code DBF

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Modules, Satndard Electronic, Gate, NAND, Digital, Key Code DBF

Modules, Satndard Electronic, Gate, NAND, Digital, Key Code DBF
Module Configuration Requirements
Figure 1. DBF module function diagram, NAND gate
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Test Procedures
Table II. Input to output relationship
Parallel Outputs
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure4. Vibration test circuit
Table III. VOUT (low-loaded) test
Figure 5. VOUT (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Figure 6. Input breakdown current test circuit for table IV
Table V. Isolation test
Figure 7. Isolation test circuit for table V
Table VI. Output voltage (low-level) test
Table VII. Output voltage (high-level) test
Table VII. Output voltage (high-level) test (cont)
Figure 8. Output voltage (low-level and high-level) test circuit for tables VI and VII
Figure 9. Logic load circuit
Table VIII. Input current (low-level) test
Table IX. Input current (high-level) test
Table X. Output short circuit current test
Figure 10. Input current (low-level and high-level) and output short circuit current test circuit
Table XI. Power supply current (low-level and high-level) test
Figure 11. Power supply current (low-level and high-level) test circuit for table XI
Table XII. Transition time (tTLH) test
Table XIII. Transition time (tTHL) test
Table XIV. Propagation delay time (tPLH) test
Table XV. Propagation delay time (tPHL) test
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit
Figure 13. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit waveforms
Table XVI. Output crosstalk (low-level) test
Table XVII. Output crosstalk (high-level) test
Figure 14. Output crosstalk (low-level and high-level) test circuit for tables XVI and XVII
Figure 15. Output crosstalk (low-level and high-level) test circuit waveforms for tables XVI and XVII
Table XVIII. Power supply transient amplitude test
Figure 16. Power supply transient amplitude test circuit for table XVIII
Figure 17. Power supply transient amplitude test circuit waveforms for table XVIII
Table XIX. Power supply filter capacitance test
Table XX. Input capacitance test
Figure 18. Power supply filter capacitance and input capacitance test circuit for tables XIX and XX
Table XXI. Output impedence (power off) check test
Table XXI. Output impedence (power off) check test (cont)
Figure 19. Output impedence (power off) check test circuit for table XXI
Standardization Document Improvement Proposal

Modules, Satndard Electronic, Gate, NAND, Digital, Key Code DBF

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