Modules, Standard Electronic, Memory, Read Only, Programmable, Digital, Key Code GYC

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Modules, Standard Electronic, Memory, Read Only, Programmable, Digital, Key Code GYC

Modules, Standard Electronic, Memory, Read Only, Programmable, Digital, Key Code GYC
Design Approval Request (DAR) Requirement
Figure 1. GYC module function diagram, programmable read only memory (PROM), dual 256-word by 8-bit
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Performance Requirements
Quality Assurance Provisions
Freeze-out Test
Module Function
Figure 2. Dynamic characteristics waveforms and module truth table
Figure 3. Operating temperature and life test circuit
Figure 4. Address counter circuit
Figure 5. Component temperature test circuit
Figure 6. Vibration test circuit
Table II. Isolation test
Figure 7. Isolation test circuit for table II
Table III. Input breakdown current
Table III. Input breakdown current (cont)
Figure 8. Input breakdown current test circuit for table III
Table IV. Output short circuit current test
Figure 9. Output short circuit current test circuit for table IV
Table V. VOUT (low-loaded) test
Figure 10. VOUT (low-loaded) test circuit for table V
Table VI. Input clamp diode voltage test
Figure 11. Input clamp diode voltage test circuit for table VI
Table VII. Input current (low-level and high-level) test
Table VII. Input current (low-level and high-level) test (cont)
Table VII. Input current (low-level and high-level) test (cont)
Table VII. Input current (low-level and high-level) test (cont)
Figure 12. Input current (low-level and high-level) test circuit for table VII
Table VIII. Power supply current test
Figure 13. Power supply current test circuit for table VIII
Table IX. Output leakage current (high-impedance state) test
Table IX. Output leakage current (high-impedance state) test (cont)
Figure 14. Output leakage current (high-impedance state) test circuit for table IX
Table X. Output voltage (Vo) level (unprogrammed) test
Figure 15. Output voltage (Vo) level (unprogrammed) test circuit for table X
Figure 16. GYC Logic load circuit
Figure 17. Static address generator
Table XI. Power supply filter capacitance test
Figure 18. Power supply filter capacitance test circuit for table XI
Table XII. Programmability test
Table XIII. Memory qualification test pattern
Table XIII. Memory qualification test pattern (cont)
Table XIII. Memory qualification test pattern (cont)
Table XIII. Memory qualification test pattern (cont)
Table XIII. Memory qualification test pattern (cont)
Table XIII. Memory qualification test pattern (cont)
Table XIV. Functional test pattern test
Figure 19. Functional test pattern test circuit for table XIV
Table XV. Static Output voltage (low-level and high-level) test
Table XV. Static Output voltage (low-level and high-level) test (cont)
Figure 20. Static Output voltage (low-level and high-level) test circuit for table XV
Table XVI. Transition time (tTLH and tTHL) test
Table XVI. Transition time (tTLH and tTHL) test (Cont)
Table XVI. Transition time (tTLH and tTHL) test (Cont)
Figure 21. Transition time (tTLH and tTHL) test circuit for table XVI
Figure 22. Transition time (tTLH and tTHL) test circuit waveforms for table XVI
Table XVII. Enable/select recovery time test
Table XVII. Enable/select recovery time test (Cont)
Table XVII. Enable/select recovery time test (Cont)
Table XVII. Enable/select recovery time test (Cont)
Figure 23. Enable/select recovery time test circuit for table XVII
Figure 24. Enable/select recovery time test circuit waveforms for table XVII
Table XVIII. Galloping read access pattern test
Figure 25. Galloping read access pattern test circuit for table XVIII
Figure 26. Galloping read access pattern program flow chart, waveforms, and program for table XVIII
Figure 26. Galloping read access pattern program flow chart, waveforms, and program for table XVIII (cont)
Figure 26. Galloping read access pattern program flow chart, waveforms, and program for table XVIII (cont)
Table XIX. Input crosstalk (low-level and high-level) test
Figure 27. Input crosstalk (low-level and high-level) test circuit for table XIX
Figure 28. Input crosstalk (low-level and high-level) test circuit waveforms for table XIX
Table XX. Power supply transient amplitude test
Figure 29. Power supply transient amplitude test circuit for table XX
Figure 30. Power supply transient amplitude test circuit waveforms for table XX
Table XXI. Input and output capacitance test
Table XXI. Input and output capacitance test (cont)
Figure 31. Input and output capacitance test circuit for table XXI
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Memory, Read Only, Programmable, Digital, Key Code GYC

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