Modules, Standard Electronic, Adder, Discrete Sum, Digital, Key Code FBG

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Modules, Standard Electronic, Adder, Discrete Sum, Digital, Key Code FBG

Modules, Standard Electronic, Adder, Discrete Sum, Digital, Key Code FBG
Failure Rate Requirements
Figure 1. FBG module function diagram, discrete sum addder
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Test Patterns
Packaging Requirements
Table II. Input to output relationship
Changes from Previous Issue
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. VOUT (low-loaded) test
Figure 5. VOUT (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Figure 6. Input breakdown current test circuit for table IV
Table V. Isolation test
Table VII. Static Output voltage (high-level) test
Figure 7. Isolation test circuit for table V
Figure 8. Static Output voltage (low-level and high-level) test circuit for tables VI and VII
Figure 9. FBG Logic load circuit
Table VIII. Input current (low-level) test
Table IX. Input current (high-level) test
Table X. Output short circuit current test
Figure 10. Input current (low-level and high-level) and output short circuit current test circuit
Figure 11. Power supply current (low-level) test circuit for table XI
Table XII. Transition time (tTLH and tTHL) test
Table XIII. Propagation delay time (tPLH and tPHL) test
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Table XIII. Propagation delay time (tPLH and tPHL) test (cont)
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit
Figure 13. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit waveforms
Table XIV. Output crosstalk (low-level) test
Table XV. Output crosstalk (high-level) test
Figure 14. Output crosstalk (low-level and high-level) test circuit for tables XIV and XV
Figure 15. Output crosstalk (low-level and high-level) test circuit waveforms for tables XIV and XV
Table XVI. Power supply transient amplitude test
Table XVIII. Input capacitance test
Figure 16. Power supply transient amplitude test circuit for table XVI
Figure 17. Power supply transient amplitude test circuit waveforms for table XVI
Figure 18. Power supply filter capacitance and input capacitance test circuit for tables XVII and XVIII
Table XIX. Functional test
Figure 19. Functional test circuit for table XIX
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Adder, Discrete Sum, Digital, Key Code FBG

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