Modules, Standard Electronic Gate, And-or-Invert, Digital, Key Code LDJ

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Modules, Standard Electronic Gate, And-or-Invert, Digital, Key Code LDJ

Modules, Standard Electronic Gate, And-or-Invert, Digital, Key Code LDJ
Input to output relationship
Parallel Outputs
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Module Configuration Requirements
Figure 1. LDJ module function diagram
Alternate Test Methods
Cross Reference of Classification
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. V out (low-loaded) test
Figure 5. V out (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Table IV. Input breakdown current test (Cont)
Figure 6. Input breakdown current test circuit for table IV
Table V. Static Output voltage (low-level) test
Table VI. Static Output voltage (high-level) test
Figure 7. Static Output voltage (low-level and high-level) test circuit for tables V and VI
Figure 8. Logic load circuit
Table VII. Input current (low-level) test
Table VII. Input current (low-level) test (cont)
Table VIII. Input current (high-level) test
Table VIII. Input current (high-level) test (cont)
Table IX. Output short circuit current test
Figure 9. Input current (low-level and high-level) and output short circuit current test circuit
Table X. Power supply current (low-level and high-level) test
Figure 10. Power supply current (low-level and high-level) test circuit for table X
Table XI. Transition time (tTLH and tTHL) test
Table XII. Propagation delay time (tPLH and tPHL) test (Cont)
Table XII. Propagation delay time (tPLH and tPHL) test (Cont)
Table XIII. Propagation delay time (tPLH and tPHL) test
Table XIII. Propagation delay time (tPLH and tPHL) test (Cont)
Figure 11. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit and waveforms
Figure 11. Transition time (tTLH and tTHL) and Propagation delay time (tPLH and tPHL) test circuit and waveforms-cont
Table XIV. Output crosstalk (low-level) test
Table XV. Output crosstalk (high-level) test
Figure 12. Output crosstalk (high-level and low-level) test circuit and waveforms for tables XIV and XV
Figure 12. Output crosstalk (high-level and low-level) test circuit and waveforms for tables XIV and XV (cont)
Table XVI. Power supply transient amplitude test
Figure 13. Power supply transient amplitude test circuit and waveforms for table XVI
Figure 13. Power supply transient amplitude test circuit and waveforms for table XVI
Table XVII. Power supply transient rise time test
Figure 14. Power supply transient rise time test circuit for table XVII
Figure 15. Power supply transient rise time test circuit waveforms for table XVII
Table XVIII. Isolation test
Figure 16. Isolation test circuit for table XVIII
Table XIX. Input capacitance test
Table XIX. Input capacitance test (Cont)
Figure 17. Input capacitance test circuit for table XIX
Table XX. Input clamp diode voltage test
Table XX. Input clamp diode voltage test (cont)
Figure 18. Input clamp diode voltage test circuit for table XX
Amendment Forms
Amendment Forms (cont)
Amendment Forms (cont)
Amendment Forms (cont)
Amendment Forms (cont)
Amendment Forms (cont)
Amendment Forms (cont)
Amendment Forms (cont)
Standardization Document Improvement Proposal
Address

Modules, Standard Electronic Gate, And-or-Invert, Digital, Key Code LDJ

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