Modules, Standard Electronic Gate, NAND, Digital, Key Code LDQ

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Modules, Standard Electronic Gate, NAND, Digital, Key Code LDQ

Modules, Standard Electronic Gate, NAND, Digital, Key Code LDQ
Failure Rate Requirements
Figure 1. LDQ module function diagram. NAND gate
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Alternate Test Methods
Input to output relationship
Power Supply Voltage
Figure 2. Operating temperature, life and burn-in test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. V out (low-loaded) test
Figure 5. V out (low-loaded) test circuit for table III
Table IV. Input breakdown current test
Table IV. Input breakdown current test (Cont)
Figure 6. Input breakdown current test circuit for table IV
Table V. Input clamp diode voltage test
Table V. Input clamp diode voltage test (cont)
Figure 7. Input clamp diode voltage test circuit for Table V
Table VI. Output voltage (low-level) test
Table VII. Output voltage (high-level) test
Table VII. Output voltage (high-level) test (Cont)
Figure 8. Output voltage (low-level and high-level) test circuit for tables VI and VII
Figure 9. LDQ Logic load circuit
Table VIII. Input current (low-level) test
Table VIII. Input current (low-level) test (cont)
Table IX. Input current (high-level) test
Table IX. Input current (high-level) test (cont)
Table X. Output short circuit current test
Figure 10. Input current (low-level and high-level) and output short circuit current test circuit
Table XI. Power supply current (low-level and high-level) test
Figure 11. Power supply current (low-level and high-level) test circuit for table XI
Table XII. Transition time (tTLH and tTHL) test
Table XIII. Propagation delay time (tPHL and tPLH) test
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPHL and tPLH) test circuit and waveforms
Figure 12. Transition time (tTLH and tTHL) and Propagation delay time (tPHL and tPLH) test circuit and waveforms-cont
Table XIV. Output crosstalk (low-level) test
Table XIV. Output crosstalk (low-level) test (Cont)
Table XV. Output crosstalk (high-level) test
Figure 13. Output crosstalk (high-level and low-level) test circuit and waveforms for tables XIV and XV
Figure 13. Output crosstalk (high-level and low-level) test circuit and waveforms for tables XIV and XV (cont)
Table XVI. Power supply transient amplitude test
Figure 14. Power supply transient amplitude test circuit and waveforms for table XVI
Figure 14. Power supply transient amplitude test circuit and waveforms for table XVI (cont)
Figure 15. Power supply transient rise time test circuit and waveforms for table XVII
Figure 15. Power supply transient rise time test circuit and waveforms for table XVII (cont)
Figure 16. Isolation test circuit for table XVIII
Table XIX. Input capacitance test
Table XIX. Input capacitance test (cont)
Figure 17. Input capacitance test circuit for table XIX
Table XX. Output capacitance (power off) check test
Table XX. Output capacitance (power off) check test (Cont)
Figure 18. Output capacitance (power off) check test circuit for table XX
Amendment Forms
Standardization Document Improvement Proposal
Address

Modules, Standard Electronic Gate, NAND, Digital, Key Code LDQ

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