Modules, Standard Electronic, Driver, NTDS (ANEW), Key Code QDR

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Modules, Standard Electronic, Driver, NTDS (ANEW), Key Code QDR

Modules, Standard Electronic, Driver, NTDS (ANEW), Key Code QDR
Table I. Input to output relationship
Correlation Requirements
Figure 1. QDR module function diagram driver, interface (NTDS anew)
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Power supply voltage
Qualification Testing
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Figure 5. QDR Logic load circuit
Table III. Frame isolation test
Figure 6. Frame Isolation test circuit for table III
Table IV. Ground pins continuity test
Figure 7. Ground pins continuity test circuit for table IV
Table V. Unused pin isolation test
Table V. Unused pin isolation test (cont)
Figure 8. Unused pin isolation test circuit for table V
Table VI. VOUT (low-loaded) test
Figure 9. VOUT (low-loaded) test circuit for table VI
Table VII. Output short circuit current test
Figure 10. Output short circuit current test circuit for table VII
Table VIII. Input breakdown current test
Figure 11. Input breakdown current test circuit for table VIII
Table IX. Static output voltage (low-level) test
Table X. Static output voltage (high-level) test
Figure 12. Static output voltage (low-level and high-level) test circuit for table IX and X
Table XI. Static output voltage (high-level) open circuit test
Figure 13. Static output voltage (high-level) open circuit test circuit for table XI
Table XII. Output terminal impedance (to line with module power removed) test
Figure 14. Output terminal impedance (to line with module power removed) test circuit for table XII
Table XIII. Input current (high-level) test
Figure 15. Input current (high-level) test circuit for table XIII
Table XIV. Input current (low-level) test
Figure 16. Input current (low-level) test circuit for table XIV
Table XV. Power supply current (low-level and high-level outputs) test
Figure 17. Power supply current (low-level and high-level outputs) test circuit for table XV
Table XVI. Transition time (tTLH and tTHL) test
Table XVI. Transition time (tTLH and tTHL) test (cont)
Table XVII. Propagation delay time (tPLH and tPHL) test
Table XVII. Propagation delay time (tPLH and tPHL) test (cont)
Table XVIII. Enable recovery time (tERL and tERH) test
Figure 18. Transition time, propagation delay time and enable recovery time test circuit
Figure 19. Transition time test circuit waveforms for table XVI
Figure 20. Propagation delay time test circuit waveform for table XVII
Figure 21. Enable recovery time test circuit waveforms for table XVIII
Table XIX. Output crosstalk (low-level and high-level) test
Figure 22. Output crosstalk (low-level and high-level) test circuit for table XIX
Figure 23. Output crosstalk test circuit waveforms for table XIX
Table XX. Power supply transient amplitude test
Figure 24. Power supply transient amplitude test circuit for table XX
Figure 25. Power supply transient amplitude test circuit waveforms for table XX
Table XXI. Power supply filter capacitance test
Figure 26. Power supply filter capacitance test circuit for table XXI
Table XXII. Input capacitance test
Figure 27. Input capacitance test circuit for table XXII
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic, Driver, NTDS (ANEW), Key Code QDR

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