Modules, Standard Electronic, Driver, Translator, Digital, Key Code DLB

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Modules, Standard Electronic, Driver, Translator, Digital, Key Code DLB

Modules, Standard Electronic, Driver, Translator, Digital, Key Code DLB
Module Configuration Requirements
Figure 1. DLB module function diagram, translator driver
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Operating Temperature Tests
Preparing Activity
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. Input breakdown curent test
Figure 5. Input breakdown curent test circuit for table III
Table IV. Isolation test
Figure 6. Isolation test circuit for table IV
Figure 7. Power sequencing test circuit for table V
Table VI. Input capacitance test
Figure 8. Input capacitance test circuit for table VI
Table VII. Output short circuit current test
Figure 9. Output short circuit current test circuit for table VII
Table VIII. Static output voltage (high-level) test
Table IX. Static output voltage (low-level) test
Figure 10. Static output voltage (high-level and low-level) test circuit for tables VIII and IX
Figure 11. DLB logic load circuit
Table X. Input current (low-level and high-level) test
Table XI. Input current (low-level and high-level) test
Figure 12. Input current (low-level and high-level) test circuit for tables X and XI
Table XII. VCC and VDD power supply current (high-level and low-level) test
Figure 13. VCC and VDD power supply current (high-level and low-level) test circuit for table XII
Table XIII. Transition time (tTLH) test
Table XIV. Transition time (tTHL) test
Table XV. Propagation delay time (tPLH) test
Table XVI. Propagation delay time (tPHL) test
Figure 14. Transition time (tTLH and tTHL) and propagation delay time (tPLH and tPHL) test circuit
Figure 15. Transition time (tTLH and tTHL) and propagation delay time (tPLH and tPHL) test circuit waveforms
Table XVII. Power supply transient amplitude test
Figure 16. Power supply transient amplitude test circuit for table XVII
Figure 17. Power supply transient amplitude test circuit waveforms for table XVII
Table XVIII. Output crosstalk (low-level) test
Table XVIII. Output crosstalk (low-level) test (Cont)
Table XVIII. Output crosstalk (low-level) test (Cont)
Table XIX. Output crosstalk (high-level) test
Table XIX. Output crosstalk (high-level) test (Cont)
Table XIX. Output crosstalk (high-level) test (Cont)
Figure 18. Output crosstalk (low-level and high-level) test circuit for tables XVIII and XIX
Figure 19. Output crosstalk (low-level and high-level) test circuit waveforms for tables XVIII and XIX
Figure 20. DLB logic load circuit for output crosstalk test
Table XX. Power supply transient rise time test
Figure 21. Power supply transient rise time test circuit for table XX
Figure 22. Power supply transient rise time test waveforms for table XX
Table XXI. Output impedance check test
Figure 23. Output impedance check test circuit for table XXI
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic, Driver, Translator, Digital, Key Code DLB

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