Modules, Standard Electronic, Flip-Flop, JK, Digiatl, Key Code QHK

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Modules, Standard Electronic, Flip-Flop, JK, Digiatl, Key Code QHK

Modules, Standard Electronic, Flip-Flop, JK, Digiatl, Key Code QHK
Failure Rate Requirements
Figure 1. QHK module function diagram, JK flip-flop
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Qualification Testing
Module Function
Table II. Input to output relationship
Figure 2. Operating temperature and life test circuit
Figure 3. Operating temperature and life test circuit waveform
Figure 4. Component temperature test circuit
Figure 5. Vibration test circuit
Table III. Isolation test
Figure 6. Isolation test circuit for table III
Figure 7. Vcc stress test circuit for table IV
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Table V. Input breakdown current test (cont)
Figure 8. Input breakdown current test circuit for table V
Table VI. Output short circuit current test
Figure 9. Output short circuit current test circuit for table VI
Table VII. Output leakage current test
Figure 10. Output leakage current test circuit for table VII
Table VIII. Input clamp diode voltage test
Table VIII. Input clamp diode voltage test (cont)
Figure 11. Input clamp diode voltage test circuit for table VIII
Table IX. Functional test
Table X. Output voltage (low-level and high-level) and input threshold check test
Table X. Output voltage (low-level and high-level) and input threshold check test (cont)
Figure 12. Functional, Output voltage (low-level and high-level) and input threshold check test circuit
Figure 13. Functional, Output voltage (low-level and high-level) and input threshold check test waveform
Figure 14. QHK logic load circuit
Table XI. Input current (high-level) test
Table XI. Input current (high-level) test (cont)
Table XI. Input current (high-level) test (cont)
Figure 15. Input current (high-level) test circuit for table XI
Table XII. Input current (low-level) test
Table XII. Input current (low-level) test (cont)
Figure 16. Input current (low-level) test circuit for table XII
Table XIII. Power supply current test
Figure 17. Power supply current test circuit for table XIII
Table XIV. Propagation delay time (tPLH and tPHL) from clock test
Table XIV. Propagation delay time (tPLH and tPHL) from clock test (cont)
Figure 18. Propagation delay time (tPLH and tPHL) from clock test circuit for table XIV
Figure 19. Propagation delay time (tPLH and tPHL) from clock test circuit waveforms for table XIV
Table XV. Propagation delay time from set and clear and minimum set and clear pulse width check test
Table XV. Propagation delay time from set and clear and minimum set and clear pulse width check test(cont)
Table XV. Propagation delay time from set and clear and minimum set and clear pulse width check test(cont)
Figure 20. Propagation delay time from set and clear and minimum set and clear pulse width check test
Figure 21. Propagation delay time from set and minimum set pulse width check test circuit waveform
Figure 22. Propagation delay time from clear and minimum clear pulse width check test circuit waveforms
Table XVI. Operating frequency and minimum clock pulse width check test
Table XVI. Operating frequency and minimum clock pulse width check test (cont)
Figure 23. Operating frequency and minimum clock pulse width check test circuit for table XVI
Figure 24. Operating frequency and minimum clock pulse width check test circuit waveforms for table XVI
Figure 25. Operating frequency and minimum clock pulse width check test circuit waveforms for table XVI
Table XVII. Output crosstalk (low-level and high-level) test
Table XVII. Output crosstalk (low-level and high-level) test (cont)
Figure 26. Output crosstalk (low-level and high-level) test circuit for table XVII
Figure 27. Output crosstalk (low-level and high-level) test circuit waveforms for table XVII
Table XVIII. Power supply transient amplitude test
Table XX. Input capacitance test
Table XX. Input capacitance test (cont)
Figure 28. Power supply transient amplitude test circuit for table XVIII
Figure 29. Power supply transient amplitude test circuit waveforms for table XVIII
Figure 30. Power supply filter capacitance test circuit for tables XIX and XX
Table XXI. Setup time test
Table XXI. Setup time test (cont)
Figure 31. Setup time test circuit for table XXI
Figure 32. Setup time test circuit waveforms for table XXI
Table XXII. Hold time test
Table XXII. Hold time test (cont)
Figure 33. Hold time test circuit for table XXII
Figure 34. Hold time test circuit waveforms for table XXII
Address
Standardization Document Improvement Proposal

Modules, Standard Electronic, Flip-Flop, JK, Digiatl, Key Code QHK

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