Modules, Digital, Standard Electronic, Interrupt Control Unit Module, Key Code SQY

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Modules, Digital, Standard Electronic, Interrupt Control Unit Module, Key Code SQY

Modules, Digital, Standard Electronic, Interrupt Control Unit Module, Key Code SQY
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (Cont)
Table I. Module electrical requirements (Cont)
Table I. Module electrical requirements (Cont)
Circuit Pin Configuration
Figure 1. SQY functional block diagram
Figure 2. SQY pin assignment
Alternate Test Methods
Figure 3. Operating temeprature and life test circuit
Figure 4. Component temperature test circuit
Figure 5. Component temperature test waveforms
Figure 6. Vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (Cont)
Input Parameters (Cont)
Output Parameters
Dynamic Parameters
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Isolation test tolerance table
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (Cont)
Input breakdown current test tolerance table
Procedure in Performing the Test
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (Cont)
Input clamp diode voltage test tolerance table
Procedure in Performing the Test
Table VII. Output short circuit current test
Output short circuit current test tolerance table
Procedure in Performing the Test
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (Cont)
Input current, high level, test tolerance table
Procedure in Performing the Test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (Cont)
Input current, low level, test tolerance table
Procedure in Performing the Test
Table X. Output voltage, high level, test
Output voltage, high level, test tolerance table
Procedure in Performing the Test
Load Capacitance
Valu eof R2 for each output load
Table XI. Output voltage, low level, test
Output voltage, low level, test tolerance table
Procedure in Performing the Test
Table XII. Output leakage current, high level, test
Output leakage current, high level, test tolerance table
Table XIII. Output leakage current, low level, test
Procedure in Performing the Test
Table XIV. Power supply current test
Table XV. Functional test
Procedure in Performing the Test
Figure 8. Input timing parameters for tables XV, XIX and XXIV
Input parametrs for figure 8
Table XVI. Dynamic test
Procedure in Performing the Test
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 9. nput pulse parameters for tables XVI, XVII and XXV
Figure 10a. Dynamic waveforms for tables XVI and XVII
Figure 10b. Dynamic waveforms for tables XVI and XVII
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply transient amplitude test
Procedure in Performing the Test
Figure 11. Power supply transient amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Table XXI. Output crosstalk, low level, test
Figure 12. Output crosstalk, high and low level, test circuit for tables XX and XXI
Figure 13. Module input timing relationship for tables XX and XXI
Input Parametrs
Figure 14. Output crosstalk test circuit waveforms, high and low level, for tables XX and XXI
Table XXII. Input capacitance test
Table XXII. Input capacitance test (cont)
Table XXII. Input capacitance test (cont)
Table XXIII. Output capacitance test
Output capacitance test tolerance table
Table XXIV. Threshold test
Procedure in Performing the Test
Table XXV. Disable time test
Disable time test tolerance table
Procedure in Performing the Test
Figure 15. Disable time test waveforms for table XXV
Appendix
Programmable Logic
Figure 1. SQY PAL booleans
Data Bus Transfers
Response Memory
Status Register
Mode Bit 3
Figure 4. Status register bit assignments
Figure 5. Mode register bit assignment
Command Register
Standardization Document Improvement Proposal

Modules, Digital, Standard Electronic, Interrupt Control Unit Module, Key Code SQY

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