Modules, Digital, Standard Electronic, 68000 Support Module, Key Code ASC

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Modules, Digital, Standard Electronic, 68000 Support Module, Key Code ASC

Modules, Digital, Standard Electronic, 68000 Support Module, Key Code ASC
Applicable Documents
Performance Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1. ASC functional block diagram
Figure 2. ASC pin assignment
Alternate Test Methods
Figure 3. ASC operating temperature and life test circuit
Figure 3. ASC operating temperature and life test circuit (cont)
Figure 4. ASC component temperature test circuit
Figure 5. ASC vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Dynamic Parameters
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Table II. Isolation test (Notes)
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Output short circuit current test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table X. Output voltage, high level, test
Output voltage, high level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Figure 6. Logic load circuit
Value of R2 for each output load
Table XI. Output voltage, low level, test
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XII. Output leakage current, high level, test
Procedure required to perform the test
Table XIII. Output leakage current, low level, test
Procedure required to perform the test
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Figure 7a. Input timing parameters for table XV
Figure 7b. Input timing parameters for table XV
Figure 7c. Input timing parameters for table XV
Input Parameters
Table XVI. Dynamic test
Procedure required to perform the test
Rise and fall times for the waveform
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 9a. Dynamic waveforms for table XVII
Figure 9b. Dynamic waveforms for table XVII
Figure 9c. Dynamic waveforms for table XVII
Figure 9d. Dynamic waveforms for table XVII
Figure 9e. Dynamic waveforms for table XVII
Figure 9f. Dynamic waveforms for table XVII
Figure 9g. Dynamic waveforms for table XVII
Figure 9h. Dynamic waveforms for table XVII
Figure 9i. Dynamic waveforms for table XVII
Figure 9j. Dynamic waveforms for table XVII
Figure 9k. Dynamic waveforms for table XVII
Figure 9l. Dynamic waveforms for table XVII
Figure 9m. Dynamic waveforms for table XVII
Figure 9n. Dynamic waveforms for table XVII
Figure 9o. Dynamic waveforms for table XVII
Figure 9p. Dynamic waveforms for table XVII
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply amplitude test
Table XIX. Power supply amplitude test (Notes)
Figure 10. Power supply amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Output crosstalk, high level, test tolerance table
Procedure required to perform the test
Table XXI. Output crosstalk, low level, test
Output crosstalk, low level, test tolerance table
Procedure required to perform the test
Figure 11. Output crosstalk, high and low level, test waveforms for tables XX and XXI
Figure 12. Output crosstalk, high and low level, test circuit for tables XX and XXI
Table XXII. Output crosstalk duration test
Table XXII. Output crosstalk duration test (Notes)
Figure 13. Output crosstalk duration test waveforms for table XXII
Table XXIII. Input capacitance test
Table XXIII. Input capacitance test (cont)
Input capacitance test tolerance table
Input capacitance test tolerance table (cont)
Table XXIV. Output capacitance test
Table XXV. Disable time test
Figure 14. Disable time test circuit for table XXV
Figure 15. Disable time test waveforms for table XXV
Figure 15. Disable time test waveforms for table XXV (cont)
Table XXVI. Threshold test
Input Threshold Levels
Appendix. Module Function
Figure 1. ASC PAL boolean equations
Table I. truth table of DTACK EN logic
Remote request latch and READ/-WRITE latch
Figure 2. Typical ASC timing for a 68000 write cycle
Standardization Document Improvement Proposal

Modules, Digital, Standard Electronic, 68000 Support Module, Key Code ASC

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