Modules,Digital, Standard Electronic, DMA Support Module, Key Code FUN

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Modules,Digital, Standard Electronic, DMA Support Module, Key Code FUN

Modules,Digital, Standard Electronic, DMA Support Module, Key Code FUN
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Quality Assurance Provisions
Figure 1. FUN functional block diagram
Figure 2. FUN pin assignment
Alternate Test Methods
Figure 3. FUN operating temperature and life test circuit
Figure 4. Logic load circuit
Value of R2 for each output load
Figure 5. FUN component temperature test circuit
Figure 6. FUN vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Output Parameters (cont)
Dynamic Parameters
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Isolation test tolerance table
Table II. Isolation test - Notes
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (cont)
Table VI. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Table VII. Output short circuit current test (cont)
Output short circuit current test tolerance table
Procedure required to perform the test
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (cont)
Table VIII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table X. Output voltage, high level, test
Table X. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Table XI. Output voltage, low level, test
Table XI. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XII. Output leakage current, high level, test
Table XII. Output leakage current, high level, test (cont)
Output leakage current, high level, test tolerance table
Procedure required to perform the test
Table XIII. Output leakage current, high level, test
Table XIII. Output leakage current, high level, test (cont)
Output leakage current, high level, test tolerance table
Procedure required to perform the test
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Figure 7. Input timingparameters for table XV
Table XVI. Dynamic test
Procedure required to perform the test
Figure 8. Sample input waveform for table XVI
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 9a. Dynamic waveforms for table XVII
Figure 9b. Dynamic waveforms for table XVII
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply transient amplitude test
Procedure required to perform the test
Figure 10. Power supply transient amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Table XX. Output crosstalk, high level, test (cont)
Table XX. Output crosstalk, high level, test (cont)
Table XXI. Output crosstalk, low level, test
Table XXI. Output crosstalk, low level, test (cont)
Table XXI. Output crosstalk, low level, test (cont)
Figure 11. Output crosstalk, high and low level, test circuit for tables XX and XXI
Figure 12. Output crosstalk, high and low level, test waveforms for tables XX and XXI
Output crosstalk, high and low level, test tolerance table
Procedure required to perform the test
Table XXII. Output crosstalk, duration, test
Table XXII. Output crosstalk, duration, test (cont)
Output crosstalk, duration, test tolerance table
Table XXII. Output crosstalk, duration, test - Notes
Figure 13. Output crosstalk, duration waveforms for table XXII
Table XXIII. Input capcitance test
Table XXIII. Input capcitance test (cont)
Table XXIII. Input capcitance test (cont)
Input capcitance test tolerance table
Table XXIV. Disable time test
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Figure 14a. Disable time test circuit for table XXIV
Figure 14b. Disable time test circuit for table XXIV
Figure 14c. Disable time test circuit for table XXIV
Figure 15a. Disable time test circuit waveform for table XXIV
Figure 15b. Disable time test circuit waveform for table XXIV
Figure 15c. Disable time test circuit waveform for table XXIV
Table XXV. Threshold test
Procedure required to perform the test
Appendix. Module Function
Module Function
Figure 1. FUN module control PAL - channel A
Figure 2. PAL internal logic diagram - channel A
Figure 3. FUN module control PAL - channel B
Figure 4. PAL internal logic diagram - channel B
Figure 5. FUN module control PAL - master channel
Figure 6. PAL internal logic diagram - master channel
Table I. Input to output relationship for buffers
Standardization Document Improvement Proposal

Modules,Digital, Standard Electronic, DMA Support Module, Key Code FUN

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