Modules, Standard Electronic, Dynamic Random Access Memory Module, Key Code CJK

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Modules, Standard Electronic, Dynamic Random Access Memory Module, Key Code CJK

Modules, Standard Electronic, Dynamic Random Access Memory Module, Key Code CJK
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Quality Assurance Provisions
Figure 1 CJK functional block diagram
Figure 2. CJK pin assignment
Alternate Test Methods
Fiogure 3. CJK operating temperature, component temperature and life test circuit
Figure 4. CJK operating temperature, component temperature and life test circuit waveforms
Input Parameters
Figure 5. CJK vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Protection
Output Parameters
Dynemic Parameters
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Table II. Isolation test (Cont)
Isolation test tolerance table
Table III. Continuity test
Table III. Continuity test (cont)
Continuity test tolerance table
Table IV. Power supply stress test
Table V. Input current, high level, test
Input current, high level, test tolerance table
Procedure required to perform the test
Table VI. Input clamp diode voltage test
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Input current, low level, test
Input current, low level, test tolerance table
Procedure required to perform the test
Table VIII. Output voltage, high level, test
Output voltage, high level, test tolerance table
Procedure required to perform the test
Load Capacitance Definitions
Value of R2 for each output load
Table IX. Output voltage, low level, test
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table X. Output leakage current, high level, test
Output leakage current, high level, test tolerance table
Procedure required to perform the test
Table XI. Output leakage current, low level, test
Output leakage current, low level, test tolerance table
Procedure required to perform the test
Table XII. Power supply current test
Table XII. Power supply current test - Notes
Table XIII. Functional test
Procedure required to perform the test
Figure 7. Input timing parameters for table XIII
Figure 7. Input timing parameters for table XIII - Notes
Table XIV. Dynamic test
Procedure required to perform the test
Figure 8. Sample input waveform for table XIV
Table XV. Dynamic parameters
Table XV. Dynamic parameters (cont)
Table XV. Dynamic parameters (cont)
Figure 9a. Dynamic waveforms for table XV
Figure 9b. Dynamic waveforms for table XV
Figure 9c. Dynamic waveforms for table XV
Figure 9d. Dynamic waveforms for table XV
Table XVI. Power supply filter capacitance test
Table XVII. Power supply transient amplitude test
Procedure required to perform the test
Figure 10. Power supply transient amplitude waveform for table XVII
Table XVIII. Input capacitance test
Input capacitance test tolerance table
Table XIX. Output capacitance test
Output capacitance test tolerance table
Table XX. Disable time test
Table XX. Disable time test (cont)
Table XX. Disable time test (cont)
Disable time test tolerance table
Disable time test circuit for table XX
Figure 12. Disable time test waveforms for table XX
Figure 12. Disable time test waveforms for table XX - Notes
Table XXI. Threshold test
Table XXI. Threshold test - Notes
Standardization Document Improvement Proposal

Modules, Standard Electronic, Dynamic Random Access Memory Module, Key Code CJK

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