Modules, Digital, Standard Electronic, Driver/Receiver Differential Module, Key Code HJN

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Modules, Digital, Standard Electronic, Driver/Receiver Differential Module, Key Code HJN

Modules, Digital, Standard Electronic, Driver/Receiver Differential Module, Key Code HJN
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1a. HJN functional block diagram
Figure 1b. HJN functional block diagram
Figure 2. HJN pin assignment
Alternate Test Methods
Figure 3. HJN operating temperature and life test circuit
Figure 3. HJN operating temperature and life test circuit - Notes
Figure 4. HJN component temperature test circuit
Figure 5. HJN vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Signal Pairs
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Functional Test Vectors
Table II. Isolation test
Figure 6. Isolation test circuit for table II
Table III. Power supply stress test
Figure 7. Vcc stress test circuit for table III
Table IV. Input breakdown current test
Table IV. Input breakdown current test (cont)
Figure 8. Input breakdown current test circuit for table IV
Table V. Output short circuit current test
Table V. Output short circuit current test (cont)
Figure 9. Output short circuit current test for table V
Figure 9. Output short circuit current test for table V - Notes
Table VI. Output leakage current, low level, test
Table VII. Output leakage current, high level, test
Table VII. Output leakage current, high level, test (cont)
Figure 10. Output leakage current test for tables VI and VII
Figure 10. Output leakage current test for tables VI and VII - Notes
Table VIII. Input clamp diode voltage test
Table VIII. Input clamp diode voltage test (cont)
Figure 11. Input clamp diode voltage test circuit for table VIII
Table IX. Output voltage, low level, test
Table IX. Output voltage, low level, test (cont)
Figure 12. Output voltage test circuit for tables IX and X
Figure 13. Logic load circuit
Figure 13. Logic load circuit (cont)
Table X. Output voltage, high level, test
Table X. Output voltage, high level, test (cont)
Table XI. Input current, low level, test
Table XI. Input current, low level, test (cont)
Table XI. Input current, low level, test (cont)
Table XI. Input current, low level, test (cont)
Table XII. Input current, high level, test
Table XII. Input current, high level, test (cont)
Table XII. Input current, high level, test (cont)
Figure 14. Input current test circuit for tables XI and XII
Figure 14. Input current test circuit for tables XI and XII - Notes
Table XIII. Power supply current (receiver and driver) test
Figure 15. Power supply current test circuit for table XIII
Table XIV. Propagation delay time (tPHL) test
Table XIV. Propagation delay time (tPHL) test (cont)
Table XIV. Propagation delay time (tPHL) test (cont)
Table XIV. Propagation delay time (tPHL) test (cont)
Table XIV. Propagation delay time (tPHL) test (cont)
Table XV. Propagation delay time (tPLH) test
Table XV. Propagation delay time (tPLH) test (cont)
Table XV. Propagation delay time (tPLH) test (cont)
Table XV. Propagation delay time (tPLH) test (cont)
Table XV. Propagation delay time (tPLH) test (cont)
Figure 16. Propagation delay time test circuit for tables XIV and XV
Figure 17. Propagation delay time test waveforms for tables XIV and XV
Table XVI. Output enable delay time (tPZH) test
Table XVI. Output enable delay time (tPZH) test (cont)
Table XVII. Output disable delay time (tPHZ) test
Table XVII. Output disable delay time (tPHZ) test (cont)
Table XVIII. Output enable delay time (tPZL) test
Table XIX. Output disable delay time (tPLZ) test
Figure 18. Output enable/disable delay time test circuit for tables XVI, XVII, XVIII and XIX
Figure 19. Output enable/disable delay time test waveforms for tables XVI, XVII, XVIII and XIX
Table XX. Functional test
Figure 20. Functional test circuit for table XX
Table XXI. Continuity test
Figure 21. Continuity test circuit for table XXI
Table XXII. Output crosstalk, low level, test
Table XXII. Output crosstalk, low level, test (cont)
Table XXIII. Output crosstalk, high level, test
Table XXIII. Output crosstalk, high level, test (cont)
Figure 22. Output crosstalk test circuit for tables XXII and XXIII
Figure 23. Output crosstalk test waveforms for tables XXII and XXIII
Table XXIV. Power supply transient amplitude test
Figure 24. Power supply transient amplitude test circuit for table XXIV
Figure 25. Power supply transient amplitude waveform for table XXIV
Table XXV. Power supply filter capacitance test
Table XXVI. Input capacitance test
Table XXVI. Input capacitance test (cont)
Table XXVI. Input capacitance test (cont)
Figure 26. Power supply filter and input capacitance test circuit for tables XXV and XXVI
Table XXVII. Terminator test
Figure 27. Terminator test circuit for table XXVII
Figure 28. Terminator test circuit waveforms for table XXVII
Standardization Document Improvement Proposal

Modules, Digital, Standard Electronic, Driver/Receiver Differential Module, Key Code HJN

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