Modules, Standard Electronic, Static Random Access Memory Module, Key Code DGG

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Modules, Standard Electronic, Static Random Access Memory Module, Key Code DGG

Modules, Standard Electronic, Static Random Access Memory Module, Key Code DGG
Applicable Documents
Module Configuration Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configurations
Figure 1. DGG functional block diagram
Figure 2. DGG pin assignment
Alternate Test Methods
Figure 3. DGG operating temperature and life test circuit
Figure 4. Operating temperature and life test waveforms
Figure 4. Operating temperature and life test waveforms - Notes
Figure 5. DGG component temperature test circuit
Figure 6. Component temperature test waveforms
Figure 6. Component temperature test waveforms - Notes
Figure 7. DGG vibration test circuit
Thermal Shock Test
Module Description
Input Parameters
Input Parameters (Cont)
Input Parameters (Cont)
Output Parameters
Output Parameters (Cont)
Output Parameters (Cont)
Dynamic Parameters
Functional Description of I/O Pins
Functional Description of I/O Pins (cont)
Functional Description of I/O Pins (cont)
Description of Tests
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Table II. Isolation test (cont)
Isolation test tolerance table
Table III. Continuity test
Table IV. Power supply stress test
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (Cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table VII. Output short circuit current test
Table VII. Output short circuit current test (cont)
Output short circuit current test tolerance table
Procedure required to perform the test
Table VIII. Input current, high level, test
Table VIII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Table IX. Input current, low level, test
Table IX. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Table X. Output voltage, high level, test
Table X. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Procedure required to perform the test
Figure 8. Logic load circuit
Value of R2 for each output load
Table XI. Output voltage, low level, test
Table XI. Output voltage, low level, test (Cont)
Output voltage, low level, test tolerance table
Procedure required to perform the test
Table XII. Output leakage current, high level, test
Output leakage current, high level, test tolerance table
Procedure required to perform the test
Table XIII. Output leakage current, low level, test
Output leakage current, low level, test tolerance table
Procedure required to perform the test
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Figure 9a. Input timing parameters for table XV (read cylcle)
Figure 9b. Input timing parameters for table XV (write cylcle)
Figure 9c. Input timing parameters for table XV (spare gates)
Figure 9c. Input timing parameters for table XV (spare gates) - Notes
Table XVI. Dynamic test
Procedure required to perform the test
Figure 10. Sample input waveform for table XVI
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Table XVII. Dynamic parameters (cont)
Figure 11a. Dynamic waveforms for table XVII (spare gates)
Figure 11b. Dynamic waveforms for table XVII (read cycle)
Figure 11c. Dynamic waveforms for table XVII (write cycle)
Table XVIII. Power supply filter capacitance test
Table XIX. Power supply transient amplitude test
Procedure required to perform the test
Figure 12. Power supply transient amplitude waveform for table XIX
Table XX. Output crosstalk, high level, test
Procedure required to perform the test
Figure 13. Output crosstalk, high and low level, test waveforms for tables XX and XXI
Figure 14. Output crosstalk, high and low level, test circuit for tables XX and XXI
Figure 15. Input waveforms for tables XX and XXI
Table XXI. Output crosstalk, low level, test
Procedure required to perform the test
Table XXII. Input capacitance test
Table XXII. Input capacitance test (cont)
Input capacitance test tolerance table
Table XXIII. Output capacitance test
Output capacitance test tolerance table
Table XXIV. Disable time test
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Table XXIV. Disable time test (cont)
Disable time test tolerance table
Figure 16. Disable time test circuit for table XXIV
Figure 17. Disable time test waveform for table XXIV
Figure 17. Disable time test waveform for table XXIV - Notes
Table XXV. Threshold test
Table XXV. Threshold test - Notes
Standardization Document Improvement Proposal

Modules, Standard Electronic, Static Random Access Memory Module, Key Code DGG

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