Modules, Standard Electronic, Converter, D/A Module, Key Code JFK

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Modules, Standard Electronic, Converter, D/A Module, Key Code JFK

Modules, Standard Electronic, Converter, D/A Module, Key Code JFK
Applicable Documents
Failure Rate Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configurations
Figure 1. JFK functional block diagram and pin assignment
Quality Assurance Provisions
Component Temperature Test
Figure 2. JFK operating temperature, component temperature, and life test circuit
Figure 3. Timing diagram for operating temperature, component temperature, and life test
Figure 4. JFK vibration test circuit
Module Description
Input Parameters
Mode and Range Selection
Functional Description of I/O Pins
Functional Test Vectors
Table II. Isolation test
Isolation test tolerance table
Isolation test circuit for table II
Table III. Continuity test
Figure 6. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 7. Power supply stress test circuit for table IV
Table V. Output short circuit current test
Table V. Output short circuit current test (cont)
Figure 8. Output short circuit current test circuit for table V
Table VI. Input current, high level, test
Input current, high level, test tolerance table
Table VII. Input current, low level, test
Input current, low level, test tolerance table
Figure 9. Input current test circuit for tables VI and VII
Table VIII. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table VIII
Table IX. Power supply current test
Procedure required to perform the test
Figure 11. Power supply current test circuit for table IX
Table X. Resistance test
Figure 12. Resistance test circuit for table X
Table XI. Bipolar accuracy test
Bipolar accuracy test tolerance table
Table XII. Unipolar accuracy test
Procedure required to perform the test
Table XIII. Integral linearity test
Table XIII. Integral linearity test (cont)
Table XIII. Integral linearity test (cont)
Integral linearity test tolerance table
Integral Linearity Test Requires Calculations
Table XIV. Differential linearity test
Table XIV. Differential linearity test (cont)
Figure 13. Circuit for unipolar and bipolar accuracy tests and linearity tests for tables XI, XII, XIII and XIV
Table XV. Power supply sensitivity test
Procedure required to perform the operation
Figure 14. Power supply sensitivity test circuit for table XV
Table XVI. Settling time test
Figure 15. Settling time test circuit for table XVI
Figure 16. Dynamic waveforms for table XVI
Figure 16. Dynamic waveforms for table XVI (cont)
Table XVII. Timing test
Figure 17. Timing test circuit for table XVII
Figure 18. Dynamic waveforms for table XVII
Standardization Document Improvement Proposal

Modules, Standard Electronic, Converter, D/A Module, Key Code JFK

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