Modules, Standard Electronic, Counter, Binary Coded Decimal, Digital, Key Code ZBZ

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Modules, Standard Electronic, Counter, Binary Coded Decimal, Digital, Key Code ZBZ

Modules, Standard Electronic, Counter, Binary Coded Decimal, Digital, Key Code ZBZ
Module Configuration Requirements
Figure 1. ZBZ module function diagram, binary coded decimal counter
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Qualification Testing
Module Description
Table II. Input to output relationship
Functional Description
Common CEP and master Reset
Figure 2. Operating temperature and life test circuit
Figure 3. Component temperature test circuit
Figure 4. Vibration test circuit
Table III. V out (low-loaded) test
Figure 5. V out (low-loaded) test circuit for table IV
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Figure 6. Input breakdown current test circuit for table V
Table VI. Input clamp diode voltage test
Table VI. Input clamp diode voltage test (Cont)
Table VII. Isolation Test
Figure 8. Isolation test circuit for table VII
Table VIII. Functional, static output voltage and input threshold check test
Table VIII. Functional, static output voltage and input threshold check test (Cont)
Table VIII. Functional, static output voltage and input threshold check test (Cont)
Table VIII. Functional, static output voltage and input threshold check test (Cont)
Table VIII. Functional, static output voltage and input threshold check test (Cont)
Figure 8. Functional, static output voltage and input threshold check test circuit for table VIII
Figure 8. Functional, static output voltage and input threshold check test circuit for table VIII (Cont)
Figure 8. Functional, static output voltage and input threshold check test circuit for table VIII (Cont)
Figure 10. ZBZ Logic load circuit
Table IX. Functional output logic states
Table X. Input current (low-level and high-level) test
Table X. Input current (low-level and high-level) test (cont)
Table X. Input current (low-level and high-level) test (cont)
Table X. Input current (low-level and high-level) test (cont)
Table X. Input current (low-level and high-level) test (cont)
Table XI. Output short circuit current test
Table XI. Output short circuit current test (cont)
Figure 11. Input current (high-level and low-level) and output short circuit current test circuit for tables X and XI
Table XII. Power supply current test
Figure 12. Power supply current test circuit for table XII
Table XIII. Input capacitance test
Table XIII. Input capacitance test (Cont)
Figure 13. Input capacitance test circuit for table XIII
Table XIV. Power supply transient amplitude test
Figure 14. Power supply transient amplitude test circuit for table XIV
Figure 15. Power supply transient amplitude test circuit waveforms for table XIV
Table XV. Propagation delay time (tPHL) test
Table XV. Propagation delay time (tPHL) test (cont)
Table XVI. Transition time (tTHL and tTLH) test
Table XVI. Transition time (tTHL and tTLH) test (cont)
Table XVII. Propagation delay time (tPLH) test
Table XVII. Propagation delay time (tPLH) test (cont)
Table XVIII. Transition time (tTLH) test
Table XVIII. Transition time (tTLH) test (cont)
Figure 16. Propagation delay time (tPLH and tPHL) and Transition time (tTLH and tTHL) test circuit
Figure 17. Propagation delay time (tPLH and tPHL) and Transition time (tTLH and tTHL) test circuit waveforms
Figure 18. Propagation delay time (tPLH) and Transition time (tTLH) test circuit waveforms for tables XVII and XVIII
Table XIX. Master reset delay time (tPHL) test
Table XIX. Master reset delay time (tPHL) test (cont)
Figure 19. Master reset delay time (tPHL) test circuit for table XIX
Figure 20. Master reset delay time (tPHL) test circuit waveforms for table XIX
Table XX. Propagation delay time (tPLH and tPHL) test
Table XX. Propagation delay time (tPLH and tPHL) test (cont)
Figure 21. Propagation delay time (tPLH and tPHL) test circuit for table XX
Figure 22. Propagation delay time (tPLH and tPHL) test circuit waveforms for table XX
Table XXI. Maximum counting frequency check test
Figure 23. Maximum counting frequency check test circuit for table XXI
Figure 24. Maximum counting frequency check test circuit waveforms for table XXI
Table XXII. Setup and hold time check test
Figure 25. Setup and hold time check test circuit for table XXII
Figure 26. Setup and hold time check test circuit waveforms for table XXII
Table XXIII. Setup and hold time check test
Table XXIII. Setup and hold time check test (Cont)
Figure 27. Setup and hold time check test circuit for table XXIII, test conditions GG1-GG15
Figure 28. Setup and hold time check test circuit for table XXIII, test conditions GG17-GG27
Figure 29. Setup and hold time check test circuit waveforms for table XXIII
Figure 30. Setup and hold time check test circuit waveforms for table XXIII
Figure 31. Setup and hold time check test circuit waveforms for table XXIII
Table XXIV. Output crosstalk (low-level and high-level) test
Table XXIV. Output crosstalk (low-level and high-level) test (cont)
Table XXIV. Output crosstalk (low-level and high-level) test (cont)
Table XXIV. Output crosstalk (low-level and high-level) test (cont)
Table XXIV. Output crosstalk (low-level and high-level) test (cont)
Figure 32. Output crosstalk (low-level and high-level) test circuit for table XXIV
Figure 33. Output crosstalk (low-level and high-level) test circuit waveforms for table XXIV
Table XXV. Power supply filter capacitance test
Figure 34. Power supply filter capacitance test circuit for table XXV
Standardization Document Improvement Proposal
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Modules, Standard Electronic, Counter, Binary Coded Decimal, Digital, Key Code ZBZ

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