Modules, Standard Electronic, IOC Common Bus Control Module, Key Code BWF

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Modules, Standard Electronic, IOC Common Bus Control Module, Key Code BWF

Modules, Standard Electronic, IOC Common Bus Control Module, Key Code BWF
Specification and Standards
Correlation Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configurations
Figure 1. BWF functional block diagram
Figure 1. BWF functional block diagram (cont)
Figure 2. BWF pin assignment
Quality Assurance Provisions
Component Temperature Test
Figure 3. BWF operating temperature and component temperature test circuit
Figure 4. BWF vibration test circuit
Figure 5. BWF life test circuit
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Output Parameters (cont)
Class I and II Dynamic Parameters
Class I and II Dynamic Parameters (cont)
Module Function
Common Bus Control
Function Control Circuits
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Functional Test Vectors
Table II. Isolation test
Table II. Isolation test (cont)
Figure 6. Isolation test circuit for table II
Table III. Continuity test
Figure 7. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 8. Vcc stress test circuit for table IV
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Output short circuit current test
Table VI. Output short circuit current test (cont)
Output short circuit current test tolerance table
Procedure required to perform the test
Table VI. Output short circuit current test (cont)
Table VII. Input current, high level, test
Table VII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Input current, high level, test tolerance table (cont)
Procedure required to perform the test
Table VIII. Input current, low level, test
Table VIII. Input current, low level, test (cont)
Input current, low level, test tolerance table
Input current, low level, test tolerance table (cont)
Procedure Required to Perform the Test
Table IX. Output Voltage, high level, test
Table IX. Output Voltage, high level, test (cont)
Output Voltage, high level, test tolerance table
Procedure Required to Perform the Test
Figure 9. Logic load circuit
Value of R2 for each output load
Table X. Output voltage, low leve, test
Table X. Output voltage, low leve, test (cont)
Output voltage, low leve, test tolerance table
Procedure Required to Perform the Test
Table XI. Output leakage current, high and low level, test
Procedure Required to Perform the Test
Table XII. Input clamp diode voltage test
Table XII. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Table XIII. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table XIII
Table XIV. Power supply current test
Table XV. Functional Test
Procedure required to perform the test
Figure 11a. Input timing parameters for table XV
Figure 11b. Input timing parameters for table XV
Figure 11b. Input timing parameters for table XV (cont)
Table XVI. Dynamic test
Table XVI. Dynamic test (Cont)
Table XVI. Dynamic test (Cont)
Table XVII. Dynamic parameters
Table XVII. Dynamic parameters (Cont)
Figure 12a. Dynamic waveforms for table XVII
Figure 12b. Dynamic waveforms for table XVII
Figure 12c. Dynamic waveforms for table XVII
Figure 12d. Dynamic waveforms for table XVII
Table XVIII. Input and output capacitance test
Table XVIII. Input and output capacitance test (cont)
Input and output capacitance test tolerance table
Input and output capacitance test tolerance table (cont)
Table XVIII. Input and output capacitance test (cont)
Figure 13. Input and output capacitance test circuit for table XVIII
Table XIX. Input clamp diode latch up test
Table XIX. Input clamp diode latch up test (cont)
Table XX. Power supply transient amplitude test
Table XX. Power supply transient amplitude test (cont)
Figure 14. Power supply transient amplitude waveform for table XX
Figure 15. Power supply transient amplitude test circuit for table XX
Standardization Document Improvement Proposal
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Modules, Standard Electronic, IOC Common Bus Control Module, Key Code BWF

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