Modules, Standard Electronic, Memory Mapped I/O Module, Key Code BWG

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Modules, Standard Electronic, Memory Mapped I/O Module, Key Code BWG

Modules, Standard Electronic, Memory Mapped I/O Module, Key Code BWG
Specification and Standards
Failure Rate Requirements
Table I. Module electrical requirements
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Table I. Module electrical requirements (cont)
Circuit Pin Configuration
Figure 1. BWG functional block diagram
Figure 1. BWG functional block diagram (cont)
Figure 2. BWG pin assignment
Alternate Test Methods
Figure 3. BWG operating temperature and component temperature test circuit
Figure 4. BWG vibration test circuit
Thermal Shock Test
Figure 5. BWG Life test circuit
Module Description
Input Parameters
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Input Parameters (cont)
Output Parameters
Output Parameters (cont)
Output Parameters (cont)
Class I and II Dynamic Parameters
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Class I and II Dynamic Parameters (cont)
Module Function
Control and Status Register
External Interrupt Register
Interface Control Logic
Description of I/O Pins
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Description of I/O Pins (cont)
Functional Test Vectors
Table II. Isolation test
Figure 6. Isolation test circuit for table II
Table III. Continuity test
Figure 7. Continuity test circuit for table III
Table IV. Power supply stress test
Figure 8. Vcc stress test circuit for table IV
Table V. Input breakdown current test
Table V. Input breakdown current test (cont)
Table V. Input breakdown current test (cont)
Input breakdown current test tolerance table
Procedure required to perform the test
Table VI. Output short circuit current test
Table VI. Output short circuit current test (cont)
Output short circuit current test tolerance table
Table VI. Output short circuit current test (cont)
Table VII. Input current, high level, test
Table VII. Input current, high level, test (cont)
Table VII. Input current, high level, test (cont)
Input current, high level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table VIII. Input current, low level, test
Table VIII. Input current, low level, test (cont)
Table VIII. Input current, low level, test (cont)
Input current, low level, test tolerance table
Procedure required to perform the test
Procedure required to perform the test (cont)
Table IX. Output voltage, high level, test
Table IX. Output voltage, high level, test (cont)
Output voltage, high level, test tolerance table
Table IX. Output voltage, high level, test (cont)
Figure 9. Logic load circuit
Value of R2 for each output load
Table X. Output voltage, low level, test
Table X. Output voltage, low level, test (cont)
Output voltage, low level, test tolerance table
Table X. Output voltage, low level, test (cont)
Table XI. Output leakage current, high and low level, test
Table XI. Output leakage current, high and low level, test (cont)
Output leakage current, high and low level, test tolerance table
Table XI. Output leakage current, high and low level, test (cont)
Table XII. Input clamp diode voltage test
Table XII. Input clamp diode voltage test (cont)
Input clamp diode voltage test tolerance table
Procedure required to perform the test
Table XIII. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table XIII
Table XIV. Power supply current test
Table XV. Functional test
Procedure required to perform the test
Table XVI. Dynamic test
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Table XVI. Dynamic test (cont)
Figure 11a. Dynamic waveforms fo rtable XVII
Figure 11b. Dynamic waveforms fo rtable XVII
Figure 11c. Dynamic waveforms fo rtable XVII
Table XVIII. Input and output capacitance test
Table XVIII. Input and output capacitance test (cont)
Table XVIII. Input and output capacitance test (cont)
Input and output capacitance test tolerance table
Input and output capacitance test tolerance table (cont)
Figure 12. Input and output capacitance test circuit for table XVIII
Table XIX. Power supply transient amplitude test
Table XIX. Power supply transient amplitude test (cont)
Figure 13. Power supply transient amplitude waveform for table XIX
Figure 14. Power supply transient amplitude test circuit for table XIX
Standardization Document Improvement Proposal

Modules, Standard Electronic, Memory Mapped I/O Module, Key Code BWG

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