Modules, Standard Electronic Memory Address Expansion Module, Key Code DWF

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Modules, Standard Electronic Memory Address Expansion Module, Key Code DWF

Modules, Standard Electronic Memory Address Expansion Module, Key Code DWF
Specifications and standards
Module configuration requirements
Table 1. Module electrical requirements
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Circuit pin configuration
Figure 1. DWF functional block diagram
Figure 1. DWF functional block diagram-cont.
Figure 2. DWF pin assignment
Multiple testing of pins
Figure 3. DWF operating temperature and component temperature test circuit
Figure 4. DWF vibration test circuit
Thermal shock test
Figure 5. DWF life test circuit
Module description
Input parameters
Input parameters-cont.
Input parameters-cont.
Input parameters-cont.
Output parameters
Output parameters-cont.
Output parameters-cont.
Output parameters-cont.
Class I and II dynamic parameters
Class I and II dynamic parameters-cont.
Write data latches
Protect decoder
Read/write control circuits
Description of I/O pins
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Functional test vectors
Table 2. Isolation test
Notes-cont.
Figure 6. Isolation test circuit for table 2
Table 3. Continuity test
Figure 7. Continuity test circuit for table 3
Table 4. Power supply stress test
Figure 8. Vcc stress test circuit for table 4
Table 5. Input breakdown current test
Table 5. Input breakdown current test-cont.
Input breakdown current test tolerance table
Input breakdown current test tolerance table-cont.
Table 6. Output short circuit current test
Table 6. Output short circuit current test-cont.
Output short circuit current test tolerance table
Notes-cont.
Table 7. Input current, high level, test
Table 7. Input current, high level, test-cont.
Table 7. Input current, high level, test-cont.
Input current, high level, test tolerance table-cont.
Notes-cont.
Table 8. Input current, low level, test
Table 8. Input current, low level, test-cont.
Input current, low level, test tolerance table
Input current, low level, test tolerance table-cont.
Notes-cont.
Table 9. Output voltage, high level, test
Table 9. Output voltage, high level, test-cont.
Output voltage, high level, test tolerance table
Notes-cont.
Figure 9. Logic load circuit
Notes-cont.
Table 10. Output voltage, low level, test
Table 10. Output voltage, low level, test-cont.
Output voltage, low level, test tolerance table
Notes-cont.
Table 11. Output leakage current, high and low level, test
Table 11. Output leakage current, high and low level, test-cont.
Table 11. Output leakage current, high and low level, test-cont.
Output leakage current, high and low level, test tolerance table
Notes-cont.
Table 12. Input clamp diode voltage test
Table 12. Input clamp diode voltage test-cont.
Input clamp diode voltage test tolerance table
Notes-cont.
Table 13. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table 13
Table 14. Power supply current test
Table 15. Functional test
Notes-cont.
Figure 11. Input timing parameters for table 15
Notes
Table 16. Dynamic test
Dynamic test tolerance table-cont.
Notes-cont.
Table 17. Dynamic parameters
Table 17. Dynamic parameters-cont.
Figure 12a. Dynamic waveforms for table 17
Figure 12b. Dynamic waveforms for table 17
Figure 12c. Dynamic waveforms for table 17
Table 18. Input and output capacitance test
Table 18. Input and output capacitance test-cont.
Table 18. Input and output capacitance test-cont.
Table 18. Input and output capacitance test-cont.
Input and output capacitance test tolerance table
Notes-cont.
Figure 13. Input and output capacitance test circuit for table 18
Table 19. input clamp diode latchup test
Notes-cont.
Table 20. Power supply transient amplitude test
Notes-cont.
Figure 14. Power supply transient amplitude waveform for table 20
Figure 15. Power supply transient amplitude test circuit for table 20
Instructions
Standardization Document Improvement Proposal

Modules, Standard Electronic Memory Address Expansion Module, Key Code DWF

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