Modules, Standard electronic Memory Interface II Module, Key Code EWD

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Modules, Standard electronic Memory Interface II Module, Key Code EWD

Modules, Standard electronic Memory Interface II Module, Key Code EWD
Specification and standards
Module configuration requirements
Table 1. Module electrical requirements
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Table 1. Module electrical requirements-cont.
Power supply voltage
Figure 1. EWD functional block diagram
Figure 2. EWD pin assignment
Operating temperature tests
Figure 3. EWD operating temperature and component temperature test circuit
Figure 4. EWD vibration test circuit
Thermal shock test
Figure 5. EWD life test circuit
Module description
Input parameters
Input parameters-cont.
Input parameters-cont.
Input parameters-cont.
Input parameters-cont.
Output parameters
Output parameters-cont.
Output parameters-cont.
Class I and II dynamic parameters
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Class I and II dynamic parameters-cont.
Module function
Memory interface initialization
Read operations
Memory address register
Configuration RAM
Loopack register
BIT control
Description of I/O pins
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Description of I/O pins-cont.
Functional test vectors
Table 2. Isolation test
Notes-cont.
Figure 6. Isolation test circuit for table II
Table 3. Continuity test
Figure 7. Continuity test circuit for table 3
Table 4. Power supply stress test
Figure 8. Vcc stress test circuit for table 4
Table 5. Input breakdown current test
Table 5. Input breakdown current test-cont.
Table 5. Input breakdown current test-cont.
Input breakdown current test tolerance table
Notes-cont.
Table 6. Output short circuit current test
Table 6. Output short circuit current test-cont.
Output short circuit current test tolerance table
Notes-cont.
Table 7. Input current, high level, test
Table 7. Input current, high level, test-cont.
Table 7. Input current, high level, test-cont.
Input current, high level, test tolerance table
Notes-cont.
Table 8. Input current, low level, test
Table 8. Input current, low level, test-cont.
Table 8. Input current, low level, test-cont.
Input current, low level, test tolerance table
Notes-cont.
Table 9. Output voltage, high level, test
Table 9. Output voltage, high level, test-cont.
Output voltage, high level, test tolerance table
Notes-cont.
Figure 9. Logic Load circuit
Notes-cont.
Table 10. Output voltage, low level, test
Table 10. Output voltage, low level, test-cont.
Output voltage, low level, test tolerance table
Notes-cont.
Table 11. Output leakage current, high and low level, test
Table 11. Output leakage current, high and low level, test-cont.
Output leakage current, hgh and low level, test tolerance table
Notes-cont.
Table 12. Input clamp diode voltage test
Table 12. Input clamp diode voltage test-cont.
Input clamp diode voltage test tolerance table
Table 13. Power supply filter capacitance test
Figure 10. Power supply filter capacitance test circuit for table 13
Table 14. Power supply current test
Table 15. Functional test
Notes-cont.
Figure 11. Input timing parameters for table 15
Notes-cont.
Table 16. Dynamic test
Notes-cont.
Notes-cont.
Table 17. Dynamic parameters
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Table 17. Dynamic parameters-cont.
Figure 12a. Dynamic waveforms for table 17
Figure 12a. Dynamic waveforms for table 17
Figure 12c. Dynamic waveforms for table 17
Table 18. Input capacitance test
Table 18. Input capacitance test-cont.
Input capacitance test tolerance table
Figure 13. Input capacitance test circuit for table 18
Table 19. Input clamp diode latchup test
Notes-cont.
Table 20. Power supply transient amplitude test
Notes-cont.
Figure 14. Power supply transient amplitude waveform for table 20
Figure 15. Power supply transient amplitude test circuit for table 20
Standardization Document Improvement Proposal
Instructions

Modules, Standard electronic Memory Interface II Module, Key Code EWD

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