TABLE III. Group A inspection Continued.
The equations take into account the test amplifier gain of 100 and other circuit constants so that the calculated
value is in table I units.
In order to remove test amplifier offset from the data values measure the offset of U1 on pin 8 with pin 9 grounded and
the device under test removed. Software subtraction techniques shall be used to correct the data.
Common mode input range conditions are exercised by grounding the signal input and swinging the power supplies to
their nominal levels minus the common mode voltage.
For example for VCM = +11.5 V, +VCC = 15 V, - 11.5 = 3.5 V and VCC = -15 V 11.5 V = -26.5 V.
With a 0 V signal input the device under test logic input is switched from 5 V to 0 V. This resets the system in the
hold mode. The test amplifier output is measured immediately after each 11.5 V change at the signal output.
Logic input step changes should have a rise time of 0.5 s or less.
E28 and E29 are measured with the device under test in the hold mode and with the hold capacitor terminal grounded.
For the hold mode step test, the first and second measurements are made with the device under test in the sample
and hold modes, respectively. The hold measurements should be made within 50 s of the device under test hold
command, especially at +125C.
High and low state logic input currents shall be measured over the common mode voltage range as shown.
The output shall be shorted to ground for 25 ms or less.
10/ Hold leakage current at 25C is determined by measuring the droop referred to the test amplifier output over a
100 ms interval.
11/ The charge current measurements on pin 7 are referenced to forced voltage of 9.5 V and 9.5 V, respectively.
12/ With worst case logic threshold voltages applied, the hold capacitor terminal output current is measured to
determine if the device is in the correct operating mode. The logic threshold levels for VTH(H) and VTH(L)
are guaranteed by measuring the hold capacitor current.
For VTH(H) hold capacitor current ≥ 1 mA. For VTH(L) hold capacitor current ≤ 10 A.
13/ Hold mode droop at 125C due to high JFET leakage current will tend to mask the data for VHS, ZO, and FRR.
To preclude this effect from happening, the test adapter sample/hold circuit, which is not at an elevated temperature,
should be used to acquire and hold the data for the measurement system.
14/ Step the signal input from 0 V to +10 V. After a delay of ≈ 100 s, generate a 100 s sample mode pulse.
The difference between the input and device under test output is monitored with a 100 V/V differential amplifier
followed by tester sample/hold circuit. Reduce the device under test sample mode pulse width until there is a
100 mV (.01%) change at the tester sample/hold output from the 100 s pulse value. The sample mode pulse
width for this condition is the acquisition time. Repeat the above procedure for input signal transitions of 10 V to 0 V,
0 V to 10 V, and 10 V to 0 V. Figure 10 shows an automatic flow chart method and figure 11 shows a simplified
manual method for determining acquisition time.
15/ Even with a Teflon hold capacitor servicing the device under test sample hold circuit, dielectric absorption errors
can occur when dynamic signals are applied to the device under test input. To minimize these errors, the error
amplifier output should be measured immediately after the test event. The tester sample and hold circuit is used to
hold the analog data for the slower responding automatic measurement system.