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Page Title:
Figure 5. Output test circuit for measuring the STS logic "1" voltage level. |
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|  MIL-M-38510/140A
NOTES:
1. RT and C are selected for an 8.0 s delay time interval.
2. DUT test circuit shall be as defined in table I.
FIGURE 5. Output test circuit for measuring the STS logic "1" voltage level.
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