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| MIL-M-38510/207E
TABLE I. Electrical performance characteristics.
Conditions 1/
Limits
Device
Units
Test
Symbol
-55C ≤ TC ≤ +125C
type
Min
Max
unless other wise specified
VCC = 4.5 V, IOH = -2 mA,
High-level output voltage
02, 04
2.4
V
VOH
VIL = 0.8 V, VIH = 2.0 V
VCC = 4.5 V, IOL = 16 mA,
01, 02,
Low-level output voltage
0.5
V
VOL
03, 04
VIL = 0.8 V, VIH = 2.0 V
VCC = 4.5 V, IIN= -10 mA,
01, 02,
Input clamp voltage
-1.5
V
VIC
03, 04
TC = +25C
Maximum collector cut-off
μA
01, 03
100
ICEX1
VCC = 5.5 V, VOH = 5.2 V
current
High impedance (off-state)
μA
02, 04
40
VCC = 5.5 V, VOH = 5.2 V
IOHZ
output high current
High impedance (off-state)
μA
02, 04
-40
VCC = 5.5 V, VOL = 0.5 V
IOLZ
output low current
01, 02,
μA
High level input current
50
IIH1
VCC = 5.5 V, VIN = 5.5 V
03, 04
VCC = 5.5 V, VIN = 4.5 V ,
100
IIH2
special programming pin
01, 02,
μA
Low level input current
-1.0
-250
IIL
VCC = 5.5 V, VIN = 0.5 V
03, 04
VCC = 5.5 V,
2/
02, 04
-10
-100
mA
Short circuit output current
IOS
VO = 0.0 V
01, 02,
VCC = 5.5 V, VIN = 0 V,
Supply current
130
mA
ICC
03, 04
outputs = open
01, 02
80
ns
Propagation delay time, high to
tPHL1
VCC = 4.5 V and 5.5 V,
low level logic, address to
CL = 30 pF, see figure 4
output
03, 04
35
01, 02
80
ns
Propagation delay time, low to
tPLH1
VCC = 4.5 V and 5.5 V,
high level logic, address to
CL = 30 pF, see figure 4
output
03, 04
35
VCC = 4.5 V and 5.5 V,
Propagation delay time, high to
01, 02
50
ns
tPHL2
low level logic, enable to output
CL = 30 pF, see figure 4
03, 04
25
Propagation delay time, low to
VCC = 4.5 V and 5.5 V,
high level logic, enable to
01, 02
50
ns
tPLH2
CL = 30 pF, see figure 4
output
03, 04
25
1/ Complete terminal conditions shall be specified in table III.
2/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test.
4
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