Microcircuits, Digital, N-Channel, Silicon-Gate Monolithic 8 BIT Microprocessor (Fixed Instruction)

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Microcircuits, Digital, N-Channel, Silicon-Gate Monolithic 8 BIT Microprocessor (Fixed Instruction)

Microcircuits, Digital, N-Channel, Silicon-Gate Monolithic 8 BIT Microprocessor (Fixed Instruction)
Design, construction, and physical dimensions
Table 1. Electrical performance characteristics
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Table 1. Electrical performance characteristics-cont.
Table 2. Electrical test requirements
High-voltage (Vzap) test of input protection circuits
Figure 1. Terminal connections
Figure 2. Functional block diagram
Table 3A. Input conditions for table 3C
Table 3A. Input conditions for table 3C-cont.
Table 3B. Functional test output conditions for subgroups 7 and 8 for table 3C-cont.
Table 3C. Group A inspection
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Table 3C. Group A inspection-cont.
Figure 3. Device pin protection circuitry
Figure 4. High voltage (Vzap) test circuits
Figure 5. Dynamic-functional load circuit
Figure 6. Burn-in and operating life-test circuit
Figure 7. Clock waveforms
Figure 8. Read cycle timing
Figure 9. Write cycle timing
Figure 10. Write cycle timing
Figure 11. Power up-reset timing
Figure 12. Processor reinitialization - reset timing
Figure 13. Interrupt timing IRQ, NMI and execution of SWI OP code
Figure 14. Normal Halt cycle
Figure 15. HALT - single instruction execute
Figure 16. Wait for interrupt instruction timing
Figure 17. TSC timing conditions
Figure 18. TSC timing
Computer generated table
Interrupt request (IRQ)
Generic test data
Ordering guidance
Standardization Document Improvement Proposal

Microcircuits, Digital, N-Channel, Silicon-Gate Monolithic 8 BIT Microprocessor (Fixed Instruction)

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